(Preliminary)

1.8V-3.3V PicoPLL, 2-PLL, 200MHz, 5 Output Clock IC

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 9/4/07 Page 1

2

3

4

5

6

7

8

9

CLK4, CSEL^

VDD

CLK3

XOUT

CLK0

VDD

CLK2, OEM^, PDB^

MSOP-10L

10

1

GND

XIN, FIN

CLK1

FEATURES

 Designed for PCB space savings with 2 low-power

Programmable PLLs and up to 5 clock outputs.

 Low-power consumption (<10µA when PDB is

activated)

 Output frequency:

o

<133MHz @ 1.8V operation

o

<166MHz @ 2.5V operation

o

<200MHz @ 3.3V operation

 Input frequency:

o

Fundamental Crystal: 10MHz - 50MHz

o

Reference Input: 1MHz - 200MHz

 Programmable I/O pins can be configured as Output

Enable (OE), Configuration Switching (CSEL), Power

Down (PDB) input, or Clock outputs.

 Single 1.8V ~ 3.3V, ± 10% power supply

 Operating temperature range from -40C to 85C

 Available in GREEN/RoHS compliant SOP-8L or

MSOP-10L packages..

DESCRIPTION

The PL612-05 is an advanced dual PLL design based

programmable clock, technology. This flexible

programmable architecture is ideal for high

performance, low-power, low-cost applications. When

using the power down (PDB) feature the PL612-05

consumes less than 10 µA of power, while its

Configuration Select (CSEL) function allows switching

of 2 programmable configurations. Besides its small

form factor and 3 or 5 outputs that can reduce overall

system costs, the PL612-05 offers superior phase

noise, jitter and power consumption performance.

PIN CONFIGURATION

^ Denotes internal pull up

BLOCK DIAGRAM

1

2

3

4

5

6

7

8

XIN, FIN

VDD

CLK0

XOUT

CLK1

GND

VDD

CLK2, OEM^, PDB^

SOP-8L