21
0832F–HIREL–02/07
e2v semiconductors SAS 2007
PC7410
Figure 9-1.
SYSCLK Input Timing Diagram
Note:
VM = Midpoint Voltage (OV
DD/2).
9.2.2
Processor Bus AC Specifications
Table 9-3 provides the processor AC timing specifications for the PC7410 as defined in Figure 9-3 on
page 23 and Figure 9-4 on page 24. Timing specifications for the L2 bus are provided in “L2 Bus AC
Specifications” on page 26.
Note:
1. All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge of the input
SYSCLK. All output specifications are measured from the midpoint of the rising edge of SYSCLK to the midpoint of the sig-
nal in question. All output timings assume a purely resistive 50
Ω load (see Figure 9-3 on page 23). Input and output timings
are measured at the pin; time-of-flight delays must be added for trace lengths, vias and connectors in the system.
2. The symbology used for timing specifications herein follows the pattern of
t(signal)(state)(reference)(state) for inputs and t(reference)(state)(signal)(state) for outputs. For example, tIVKH symbolizes the time input signals
(I) reach the valid state (V) relative to the SYSCLK reference (K) going to the high (H) state or input setup time. And t
KHOV
symbolizes the time from SYSCLK (K) going high (H) until outputs (O) are valid (V) or output valid time. Input hold time can
be read as the time that the input signal (I) went invalid (X) with respect to the rising clock edge (KH) - note the position of
the reference and its state for inputs -and output hold time can be read as the time from the rising edge (KH) until the output
went invalid (OX).
3. The setup and hold time is with respect to the rising edge of HRESET (see Figure 9-4 on page 24).
SYSCLK
VM
VM
VM
CVIL
CVIH
tKHKL
tSYSCLK
tKR
tKF
Table 9-3.
Processor Bus AC Timing Specifications
(1) at V
DD = AVDD = 1.8V ± 100 mV;
-55°C
≤T
J ≤125°C, OVDD = 1.8V ± 100 mV
Symbol(2)
Parameter
400, 450, 500 MHz
Unit
Min
Max
tIVKH
Input Setup
1.0
–
ns
tIXKH
Input Hold
0–
ns
tKHTSV
tKHARV
t
KHOV
Output Valid Times:(7)(8)
TS
ARTRY/SHD0/SHD1
All Other Outputs
–
–
–
3.0
2.3
3.0
ns
t
KHTSX
t
KHARX
tKHOX
Output Hold Times:(7)(12)
TS
ARTRY/SHD0/SHD1
All Other Outputs
0.5
0.5
0.5
–
–
–
ns
t
KHOE
(11)
SYSCLK to Output Enable
0.5
–
ns
t
KHOZ
SYSCLK to Output High Impedance (all except ABB/AMON[0], ARTRY/SHD,
DBB/DMON[0]), SHD0, SHD1)
–3.5
ns
t
KHABPZ
(5)(9)(11)
SYSCLK to ABB/AMON[0], DBB/DMON[0] High Impedance after precharge
–
1
t
SYSCLK
t
KHARP
(5)(10)(11)
Maximum Delay to ARTRY/SHD0/SHD1 Precharge
–
1
t
SYSCLK
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