M27V256

2/15

Figure 2B. LCC Pin Connections

Warning: NC = Not Connected, DU = Dont’t Use.

AI01910

A8

A10

17

A0

NC

Q0

A6

A3

A2

A1

A5

A4

9

A9

1

A11

Q6

Q7

32

M27V256

NC

G

E

25

Figure 2A. DIP Pin Connections

A1

A0

Q0

A7

A4

A3

A2

A6

A5

A13

A10

A8

A9

Q7

A14

A11

G

E

Q5

Q1

Q2

Q3

VSS

Q4

Q6

A12

VPP

VCC

AI01909

M27V256

8

1

2

3

4

5

6

7

9

10

11

12

13

14

16

15

28

27

26

25

24

23

22

21

20

19

18

17

For applications where the content is programmed

only one time and erasure is not required, the

M27V256 is offered in PDIP28, PLCC32 and

TSOP28 (8 x 13.4 mm) packages.

DEVICE OPERATION

The modes of operation of the M27V256 are listed

in the Operating Modes. A single power supply is

required in the read mode. All inputs are TTL lev-

Signature.

Read Mode

The M27V256 has two control functions, both of

which must be logically active in order to obtain

data at the outputs. Chip Enable (E) is the power

control and should be used for device selection.

Output Enable (G) is the output control and should

be used to gate data to the output pins, indepen-

dent of device selection. Assuming that the ad-

dresses are stable, the address access time

E has been low and the addresses have been sta-

Figure 2C. TSOP Pin Connections

A1

A0

Q0

A5

A2

A4

A3

A9

A11

Q7

A8

G

E

Q5

Q1

Q2

Q3

Q4

Q6

A13

A14

A12

A6

VPP

VCC

A7

AI01911

M27V256

28

1

22

78

14

15

21

VSS

A10