M27V320 datasheet(2/15 Pages) STMICROELECTRONICS

2 / 15 page

M27V320

2/15

Figure 3. TSOP Connections

AI05854

M27V320

GVPP

VSS

A13

VSS

A14

A15

A12

A16

BYTE

Q15A–1

VCC

Q11

Q14

A19

A18

A20

Q13

A11

A10

Q10

Q12

A17

VSS

VCC

VSS

Figure 2. SO Connections

GVPP

VSS

A13

VSS

A14

A15

A12

A16

BYTE

Q15A–1

VCC

Q11

Q14

A19

A18

A20

AI05853

M27V320

Q13

A11

A10

Q10

Q12

A17

Table 1. Signal Names

A0-A20

Address Inputs

Q0-Q7

Data Outputs

Q8-Q14

Data Outputs

Q15A–1

Data Output / Address Input

Chip Enable

GVPP

Output Enable / Program Supply

BYTE

Byte-Wide Select

VCC

Supply Voltage

VSS

Ground

Not Connected Internally

DEVICE OPERATION

The operating modes of the M27V320 are listed in

the Operating Modes Table. A single power supply

is required in the read mode. All inputs are TTL

compatible except for VPP and 12V on A9 for the

Electronic Signature.

Read Mode

The M27V320 has two organisations, Word-wide

and Byte-wide. The organisation is selected by the

signal level on the BYTE pin. When BYTE is at VIH

the Word-wide organisation is selected and the

Q15A–1 pin is used for Q15 Data Output. When

the BYTE pin is at VIL the Byte-wide organisation

is selected and the Q15A–1 pin is used for the Ad-

dress Input A–1. When the memory is logically re-

garded as 16 bit wide, but read in the Byte-wide

organisation, then with A–1 at VIL the lower 8 bits

of the 16 bit data are selected and with A–1 at VIH

the upper 8 bits of the 16 bit data are selected.

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