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APPLICATION INFORMATION

I

SDA

SCL

Start

Condition

Stop

Condition

SDA

SCL

GENERAL I

SN75DP129

SLAS583A – JANUARY 2008 – REVISED MARCH 2008

by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000). The bus consists of a data line

(SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines are pulled

device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for

generating the SCL signal and device addresses. The master also generates specific conditions that indicate the

START and STOP of data transfer. A slave device receives and/or transmits data on the bus under control of the

master device. The SN75DP129 works as a slave and supports the standard mode transfer (100 kbps) as

The basic access cycle consists of the following:

• A start condition

• A slave address cycle

• Any number of data cycles

• A stop condition

• The master initiates data transfer by generating a start condition. The start condition is when a high-to-low

should recognize a start condition.

• The master generates the SCL pulses and transmits the 7-bit address and the read/write direction bit R/W on

the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires

the SDA line to be stable during the entire high period of the clock pulse (see Figure 24). All devices

recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave

device with a matching address generates an acknowledge (see Figure 25) by pulling the SDA line low during

the entire high period of the ninth SCL cycle. On detecting this acknowledge, the master knows that a

communication link with a slave has been established.

• The master generates further SCL cycles to transmit data to the slave (R/W bit 0) or receive data from the

slave (R/W bit 1). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an

acknowledge signal can either be generated by the master or by the slave, depending on which one is the

receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long

as necessary (see Figure 26).

• To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low

to high while the SCL line is high (see Figure 26). This releases the bus and stops the communication link

stop condition, all devices know that the bus is released, and they wait for a start condition ,followed by a

matching address.

Copyright © 2008, Texas Instruments Incorporated

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