ST7L05 datasheet(49/104 Pages) STMICROELECTRONICS

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ST7L05, ST7L09

49/104

12-BIT AUTORELOAD TIMER (Cont’d)

Figure 30. PWM Signal Example

Output Compare Mode

To use this function, the OE bit must be 0, other-

wise the compare is done with the shadow register

instead of the DCRx register. Software must then

write a 12-bit value in the DCR0H and DCR0L reg-

isters. This value is loaded immediately (without

waiting for an OVF event).

The DCR0H must be written first, the output com-

pare function starts only when the DCR0L value is

written.

When the 12-bit upcounter (CNTR) reaches the

value stored in the DCR0H and DCR0L registers,

the CMPF0 bit in the PWM0CSR register is set

and an interrupt request is generated if the CMPIE

bit is set.

Note: The output compare function is only availa-

ble for DCRx values other than 0 (reset value).

Caution: At each OVF event, the DCRx value is

written in a shadow register, even if the DCR0L

value has not yet been written (in this case, the

shadow register will contain the new DCR0H value

and the old DCR0L value), then:

– If OE = 1 (PWM mode): The compare is done be-

tween the timer counter and the shadow register

(and not DCRx).

– if OE = 0 (OCMP mode): The compare is done

between the timer counter and DCRx. There is

no PWM signal.

The compare between DCRx or the shadow regis-

ter and the timer counter is locked until DCR0L is

written.

11.2.4 Low Power Modes

11.2.5 Interrupts

Notes:

1. The interrupt events are connected to separate inter-

rupt vectors (see Interrupts chapter).

They generate an interrupt if the enable bit is set in the

ATCSR register and the interrupt mask in the CC register

is reset (RIM instruction).

2. Only if CK0 = 1 and CK1 = 0.

COUNTER

FFDh

FFEh

FFFh

FFDh

FFEh

FFFh

FFDh

FFEh

DCR0 = FFEh

ATR = FFDh

fCOUNTER

Mode

Description

SLOW

The input frequency is divided by 32

WAIT

No effect on AT timer

ACTIVE HALT

AT timer halted except if CK0 = 1,

CK1 = 0 and OVFIE = 1

HALT

AT timer halted

Interrupt

Event1)

Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt

Exit

from

Active

Halt

Overflow

Event

OVF

OVFIE

Yes

Yes2)

CMP Event

CMPFx CMPIE

Yes

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