M27W032 datasheet(9/23 Pages) STMICROELECTRONICS

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M27W032

Start Address), that indicates to the PC that the

Program Phase has to continue. A0 to A16 are

‘don’t care’.

3. Finally, after all Words have been programmed,

a Bus Write operation (the (n+1)th) with a Final

Address, FA (A17 or a higher address pin

different from the Start Address), ends the

Program Phase.

The memory is now set to enter the Verify Phase.

Verify Phase. The Verify Phase is similar to the

Program Phase in that all Words must be resent to

the memory for them to be checked against the

programmed data.

Before any Bus Write Operation of the Verify

Phase, the Status Register must be read in order

to check that the PC is ready for the next operation

or if the reprogram of the location has failed (see

Table 6 and Figure 6).

Three successive steps are required to execute

the Verify Phase of the command:

1. The first Bus Write operation of the Verify Phase

latches the Start Address and the Word to be

verified.

2. Each subsequent Bus Write operation latches

the next Word to be verified and automatically

increments the internal Address Bus. As in the

Program Phase, it is not necessary to provide

the address of the location to be programmed

but only a Continue Address, CA (A17 to A20

equal to the Start Address).

3. Finally, after all Words have been verified, a Bus

Write cycle with a Final Address, FA (A17 or a

higher address pin different from the Start

Address) ends the Verify Phase.

Exit Phase. After the Verify Phase ends, the Sta-

tus Register must be read to check if the command

has successfully completed or not (see Table 6

and Figure 6).

If the Verify Phase is successful, the memory re-

turns to Read mode and DQ6 stops toggling.

If the PC fails to reprogram a given location, the

Verify Phase terminates, DQ6 continues toggling

and error bit DQ5 is set in the Status Register. If

the error is due to a VPP failure DQ4 is also set.

When the operation fails a Read/Reset command

must be issued to return the device to Read mode.

During the Multiple Word Program operation the

memory will ignore all commands. It is not possible

to issue any command to abort or pause the oper-

ation. Typical program times are given in Table 5.

Bus Read operations during the program opera-

tion will output the Status Register on the Data In-

puts/Outputs. See the section on the Status

Note that the Multiple Word Program command

cannot change a bit set to ’0’ back to ’1’.

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