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ESSDC64 数据表(PDF) 5 Page - Eorex Corporation |
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ESSDC64 数据表(HTML) 5 Page - Eorex Corporation |
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5 / 6 page ![]() 64MB/128MB/256MB/512MB Secure Digital Card Eorex Corporation www.eorex.com 5/6 5. Bus Timing Parameter Symbol Min Max Unit Remark Clock CLK (All values are referred to min (VIH) and max (VIL) Clock frequency Data Transfer Mode fpp 0 20 MHz CL<100pF,(7 cards) Clock frequency Identification Mode (The low freq. is required for MultiMediaCard compatibility.) fOD 0 400 KHz CL<250pF,(21 cards) tWL 10 ns CL≤100pF, (7 cards) Clock low time 50 ns CL≤250pF, (21 cards) tWH 10 ns CL≤100pF, (7 cards) Clock high time 50 ns CL≤250pF, (21 cards) tTLH 10 ns CL≤100pF, (7 cards) Clock rise time 50 ns CL≤250pF, (21 cards) tTHL 10 ns CL≤100pF, (7 cards) Clock fall time 50 ns CL≤250pF, (21 cards) Inputs CMD, DAT (referenced to CLK) Input set-up time fISU 5 ns CL<25pF,(1 cards) Input hold time fIH 5 ns CL<25pF,(1 cards) Outputs CMD, DAT (referenced to CLK) Output Delay time fODLY 0 14 ns CL<25pF,(1 cards) |
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