M28256

256 Kbit (32Kb x8) Parallel EEPROM

with Software Data Protection

PRELIMINARY DATA

January 1999

1/21

This is preliminary information on a new product now in developmentor undergoing evaluation . Detail s are subject to change without notice.

AI01885

15

A0-A14

W

DQ0-DQ7

VCC

M28256

G

E

VSS

8

Figure 1. Logic Diagram

28

1

PDIP28 (BS)

PLCC32 (KA)

A0-A14

Address Input

DQ0-DQ7

Data Input / Output

W

Write Enable

E

Chip Enable

G

Output Enable

Supply Voltage

Ground

Table 1. Signal Names

FAST ACCESS TIME:

– 90ns at 5V

– 120ns at 3V

SINGLE SUPPLY VOLTAGE:

–5V

± 10% for M28256

– 2.7V to 3.6V for M28256-xxW

LOW POWER CONSUMPTION

FAST WRITE CYCLE:

– 64 Bytes Page Write Operation

– Byte or Page Write Cycle

ENHANCED END of WRITE DETECTION:

– Data Polling

– Toggle Bit

STATUS REGISTER

HIGH RELIABILITY DOUBLE POLYSILICON,

CMOS TECHNOLOGY:

– Endurance >100,000 Erase/Write Cycles

– Data Retention >10 Years

JEDEC APPROVED BYTEWIDE PIN OUT

ADDRESS and DATA LATCHED ON-CHIP

SOFTWARE DATA PROTECTION

DESCRIPTION

The M28256 and M28256-Ware 32K x8 low power

Parallel EEPROM fabricatedwith STMicroelectron-

ics proprietary double polysilicon CMOS technol-

ogy.

TSOP28 (NS)

8 x13.4mm

28

1

SO28 (MS)

300 mils