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ST7SCR 数据表(PDF) 81 Page - STMicroelectronics |
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ST7SCR 数据表(HTML) 81 Page - STMicroelectronics |
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81 / 101 page  ST7SCR 81/101 14.3 SUPPLY AND RESET CHARACTERISTICS (T = 0 to +70oC, VDD - VSS = 5.5V unless otherwise specified) Note 1 : Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested. 14.4 CLOCK AND TIMING CHARACTERISTICS 14.4.1 General Timings (Operating conditions T A = 0 to +70°C unless otherwise specified) * ∆t INST is the number of tCPU to finish the current instruction execution. 14.4.2 External Clock Source Notes: 1. Data based on typical application software. 2. Time measured between interrupt event and interrupt vector fetch. ∆t c(INST) is the number of tCPU cycles needed to finish the current instruction execution. 3. Data based on design simulation and/or technology characteristics, not tested in production. LOW VOLTAGE DETECTOR AND SUPERVISOR (LVDS) Symbol Parameter Conditions Min Typ Max Unit VIT+ Reset release threshold (VDD rising) 3.7 3.9 V VIT- Reset generation threshold (VDD falling) 3.3 3.5 V Vhys Hysteresis VIT+ - VIT- 1) 200 mV VtPOR VDD rise time rate 1) 20 ms/V Symbol Parameter Conditions Min Typ 1) Max Unit tc(INST) Instruction cycle time 23 12 tCPU fCPU=4MHz 500 750 3000 ns tv(IT) Interrupt reaction time 2) tv(IT) = ∆tc(INST) + 10 10 22 tCPU fCPU=4MHz 2.5 5.5 µs Symbol Parameter Conditions Min Typ Max Unit VOSCINH OSCIN input pin high level voltage see Figure 40 0.7xVDD VDD V VOSCINL OSCIN input pin low level voltage VSS 0.3xVDD tw(OSCINH) tw(OSCINL) OSCIN high or low time 3) 15 ns tr(OSCIN) tf(OSCIN) OSCIN rise or fall time 3) 15 IL OSCx Input leakage current VSS≤VIN≤VDD ±1 µA |
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