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STM32F101X4 数据表(PDF) 13 Page - STMicroelectronics |
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STM32F101X4 数据表(HTML) 13 Page - STMicroelectronics |
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13 / 87 page ![]() DocID15058 Rev 6 13/87 STM32F101x4, STM32F101x6 Description 86 Figure 2. Clock tree 1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is 36 MHz. 2. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz or 28 MHz. HSE OSC 4-16 MHz OSC_IN OSC_OUT OSC32_IN OSC32_OUT LSE OSC 32.768 kHz HSI RC 8 MHz LSI RC 40 kHz to Independent Watchdog (IWDG) PLL x2, x3, x4 PLLMUL Legend: MCO Clock Output Main PLLXTPRE /2 ..., x16 AHB Prescaler /1, 2..512 /2 PLLCLK HSI HSE APB1 Prescaler /1, 2, 4, 8, 16 ADC Prescaler /2, 4, 6, 8 ADCCLK PCLK1 HCLK PLLCLK to AHB bus, core, memory and DMA to TIM2, TIM3 to ADC LSE LSI HSI /128 /2 HSI HSE peripherals to APB1 Peripheral Clock Enable (13 bits) Enable (3 bits) Peripheral Clock APB2 Prescaler /1, 2, 4, 8, 16 PCLK2 peripherals to APB2 Peripheral Clock Enable (11 bits) 36 MHz max 36 MHz max to RTC PLLSRC SW MCO CSS to Cortex System timer /8 Clock Enable (3 bits) SYSCLK RTCCLK RTCSEL[1:0] TIMXCLK IWDGCLK SYSCLK FCLK Cortex free running clock TIM2, TIM3 If (APB1 prescaler =1) x1 else x2 HSE = high-speed external clock signal HSI = high-speed internal clock signal LSI = low-speed internal clock signal LSE = low-speed external clock signal ai15174 36 MHz max 36 MHz max |
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