MSC8103 datasheet(2/104 Pages) FREESCALE

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MSC8103 Network Digital Signal Processor, Rev. 11

Freescale Semiconductor

Table of Contents

MSC8103 Features .................................................................................................................................................................................... iii

Target Applications .....................................................................................................................................................................................iv

Product Documentation ..............................................................................................................................................................................iv

Chapter 1

Signals/Connections

1.1

Power Signals......................................................................................................................................................................... 1-4

1.2

Clock Signals ......................................................................................................................................................................... 1-4

1.3

Reset, Configuration, and EOnCE Event Signals .................................................................................................................. 1-5

1.4

System Bus, HDI16, and Interrupt Signals............................................................................................................................ 1-6

1.5

Memory Controller Signals ................................................................................................................................................. 1-13

1.6

CPM Ports............................................................................................................................................................................ 1-15

1.7

JTAG Test Access Port Signals............................................................................................................................................ 1-36

1.8

Reserved Signals .................................................................................................................................................................. 1-36

Chapter 2

Physical and Electrical Specifications

2.1

Absolute Maximum Ratings .................................................................................................................................................. 2-1

2.2

Recommended Operating Conditions .................................................................................................................................... 2-2

2.3

Thermal Characteristics ......................................................................................................................................................... 2-2

2.4

DC Electrical Characteristics................................................................................................................................................. 2-3

2.5

Clock Configuration............................................................................................................................................................... 2-4

2.6

AC Timings ............................................................................................................................................................................ 2-7

Chapter 3

Packaging

3.1

FC-PBGA Package Description............................................................................................................................................. 3-1

3.2

Lidded FC-PBGA Package Mechanical Drawing ............................................................................................................... 3-31

Chapter 4

Design Considerations

4.1

Thermal Design Considerations............................................................................................................................................. 4-1

4.2

Electrical Design Considerations........................................................................................................................................... 4-1

4.3

Power Considerations ............................................................................................................................................................ 4-2

4.4

Layout Practices..................................................................................................................................................................... 4-3

Ordering and Contact Information ............................................................................................................................... Back Cover

Data Sheet Conventions

pin and pin-

out

Although the device package does not have pins, the term pins and pin-out are used for

convenience and indicate specific signal locations within the ball-grid array.

OVERBAR

Used to indicate a signal that is active when pulled low (For example, the RESET pin is active

when low.)

“asserted”

Means that a high true (active high) signal is high or that a low true (active low) signal is low

“deasserted”

Means that a high true (active high) signal is low or that a low true (active low) signal is high

Examples:

Signal/Symbol

Logic State

Signal State

Voltage

True

Asserted

VIL/VOL

False

Deasserted

VIH/VOH

True

Asserted

VIH/VOH

False

Deasserted

VIL/VOL

Note:

Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.

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