M41ST84WMQ datasheet(12/31 Pages) STMICROELECTRONICS

12 / 31 page

M41ST84Y, M41ST84W

12/31

READ Mode

In this mode the master reads the M41ST84Y/W

slave after setting the slave address (see Figure

12, page 12). Following the WRITE Mode Control

Bit (R/W=0) and the Acknowledge Bit, the word

address ‘An’ is written to the on-chip address

pointer. Next the START condition and slave ad-

dress are repeated followed by the READ Mode

Control Bit (R/W=1). At this point the master trans-

mitter becomes the master receiver. The data byte

which was addressed will be transmitted and the

master receiver will send an Acknowledge Bit to

the slave transmitter. The address pointer is only

incremented on reception of an Acknowledge

Clock. The M41ST84Y/W slave transmitter will

now place the data byte at address An+1 on the

bus, the master receiver reads and acknowledges

the

new

byte

and

the

address

pointer

incremented to “An+2.”

This cycle of reading consecutive addresses will

continue until the master receiver sends a STOP

condition to the slave transmitter (see Figure 13,

page 12).

The system-to-user transfer of clock data will be

halted whenever the address being read is a clock

address (00h to 07h). The update will resume ei-

ther due to a Stop Condition or when the pointer

increments to a non-clock or RAM address.

Note: This is true both in READ Mode and WRITE

Mode.

An alternate READ Mode may also be implement-

ed whereby the master reads the M41ST84Y/W

slave without first writing to the (volatile) address

pointer. The first address that is read is the last

one stored in the pointer (see Figure 14, page 13).

Figure 12. Slave Address Location

Figure 13. READ Mode Sequence

AI00602

R/W

SLAVE ADDRESS

START

100

AI00899

BUS ACTIVITY:

SDA LINE

BUS ACTIVITY:

MASTER

DATA n

DATA n+1

DATA n+X

WORD

ADDRESS (An)

SLAVE

ADDRESS

SLAVE

ADDRESS

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