Clock operation

M41T56

16/28

Figure 12.

Crystal accuracy across temperature

Figure 13.

Clock calibration

3.2

Output driver pin

When the FT Bit is not set, the FT/OUT pin becomes an output driver that reflects the

contents of D7 of the Control Register. In other words, when D6 of location 7 is a '0' and D7

of location 7 is a '0' and then the FT/OUT pin will be driven low.

Note:

The FT/OUT pin is open drain which requires an external pull-up resistor.

3.3

Initial power-on defaults

Upon initial application of power to the device, the FT Bit will be set to a '0' and the OUT Bit

will be set to a '1.' All other Register bits will initially power-on in a random state.

AI00999b

–160

0

10203040506070

Frequency (ppm)

Temperature

°C

80

–10

–20

–30

–40

–100

–120

–140

–40

–60

–80

20

0

–20

∆F

2

K = –0.036 ppm/

F

AI00594B

NORMAL

POSITIVE

CALIBRATION

NEGATIVE

CALIBRATION