M41T80

16/20

Century Bit

Bits D7 and D6 of Clock Register 03h contain the

CENTURY ENABLE Bit (CEB) and the CENTURY

Bit (CB). Setting CEB to a '1' will cause CB to tog-

gle, either from a '0' to '1' or from '1' to '0' at the turn

of the century (depending upon its initial state). If

CEB is set to a '0,' CB will not toggle.

Output Driver Pin

When the AFE Bit and SQWE Bit are not set, the

IRQ/OUT/SQW pin becomes an output driver that

reflects the contents of D7 of the Control Register.

In other words, when D7 (OUT Bit) of address lo-

cation 08h is a '0,' then the IRQ/OUT/SQW pin will

be driven low.

Note: The IRQ/OUT/SQW pin is an open drain

which requires an external pull-up resistor.

Preferred Power-on Default

When powering the device up from ground (0V),

the following register bits are set to a '0' state: ST;

AFE; and SQWE. The following bits are set to a '1'

state: OUT and 32kE (see Table 11, page 16).

Table 11. Preferred Power-on Default Values

Condition

ST

Out

AFE

SQWE

32kE

01

00

1