M41T256YMT7F datasheet(12/27 Pages) STMICROELECTRONICS

12 / 27 page

M41T256Y

12/27

Data Retention Mode

With valid VCC applied, the M41T256Y can be ac-

cessed as described above with READ or WRITE

Cycles. Should the supply voltage decay, the

M41T256Y will automatically deselect, write pro-

tecting itself when VCC falls between VPFD (max)

and VPFD (min). This is accomplished by internally

inhibiting access to the clock registers. At this

time, the Reset pin (RST) is driven active and will

remain active until VCC returns to nominal levels.

When VCC falls below the Battery Back-up

Switchover Voltage (VSO), power input is switched

from the VCC pin to the external battery and the

clock registers and SRAM are maintained from the

attached battery supply.

All outputs become high impedance. On power up,

when VCC returns to a nominal value, write protec-

tion continues for tREC. The RST signal also re-

mains

active

during

this

time

(see

Figure

17., page 21).

For a further more detailed review of lifetime calcu-

lations, please see Application Note AN1012.

Sleep Mode

In order to minimize the battery current draw while

in storage, the M41T256Y provides the user with a

battery “Sleep Mode,” which disconnects the RAM

memory array from the external Lithium battery

normally used to provide non-volatile operation in

the absence of VCC. This can significantly extend

the lifetime of the battery, when non-volatile oper-

ation is not needed.

Note: The Sleep Mode will remove power from the

RAM array only and not affect the data retention of

the TIMEKEEPER Registers (7FF0h through

7FFFh - this includes the Calibration Register).

The Sleep Mode (SLP) Bit located in register

7FF8h (D6), must be set to a '1' by the user while

the device is powered by VCC. This will “arm” the

Sleep Mode latch, but not actually disconnect the

RAM array from power until the next power-down

cycle. This protects the user from immediate data

loss in the event he inadvertently sets the SLP Bit.

Once VCC falls below VSO (VBAT), the Sleep Mode

circuit will be engaged and the RAM array will be

isolated from the battery, resulting in both a lower

battery current, and a loss of RAM data.

Note: Upon initial battery attach or initial power

application without the battery, the state of the

SLP Bit will be undetermined. Therefore, the SLP

Bit should be initialized to '0' by the user.

Additional current reduction can be achieved by

setting the STOP (ST) Bit in register 7FF9h (D7),

turning off the clock oscillator. This combination

will result in the longest possible battery life, but

also loss of time and data. When the device is

again powered-up, the user should first read the

SLP Bit to determine if the device is currently in

Sleep Mode, then reset the bit to '0' in order to dis-

able the Sleep Mode (this will NOT be automatical-

ly taken care of during the power-up).

Note: See AN1570, “M41T256Y Sleep Mode

Function” for more information on Sleep Mode and

battery lifetimes.

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