M41ST85YMX6 datasheet(21/34 Pages) STMICROELECTRONICS

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M41ST85Y, M41ST85W

Power-fail INPUT/OUTPUT

The Power-Fail Input (PFI) is compared to an in-

ternal reference voltage (1.25V). If PFI is less than

the power-fail threshold (VPFI), the Power-Fail

Output (PFO) will go low. This function is intended

for use as an undervoltage detector to signal a fail-

ing power supply. Typically PFI is connected

through an external voltage divider (see Figure

7., page 7) to either the unregulated DC input (if it

is available) or the regulated output of the VCC reg-

ulator. The voltage divider can be set up such that

the voltage at PFI falls below VPFI several millisec-

onds before the regulated VCC input to the

M41ST85Y/W or the microprocessor drops below

the minimum operating voltage.

During battery back-up, the power-fail comparator

turns off and PFO goes (or remains) low. This oc-

curs after VCC drops below VPFD(min). When pow-

er returns, PFO is forced high, irrespective of VPFI

for the write protect time (trec), which is the time

from VPFD(max) until the inputs are recognized. At

the end of this time, the power-fail comparator is

enabled and PFO follows PFI. If the comparator is

unused, PFI should be connected to VSS and PFO

left unconnected.

Century Bit

Bits D7 and D6 of Clock Register 03h contain the

CENTURY ENABLE Bit (CEB) and the CENTURY

Bit (CB). Setting CEB to a '1' will cause CB to tog-

gle, either from a '0' to '1' or from '1' to '0' at the turn

of the century (depending upon its initial state). If

CEB is set to a '0,' CB will not toggle.

Output Driver Pin

When the FT Bit, AFE Bit and watchdog register

are not set, the IRQ/FT/OUT pin becomes an out-

put driver that reflects the contents of D7 of the

Control Register. In other words, when D7 (OUT

Bit) and D6 (FT Bit) of address location 08h are a

'0,' then the IRQ/FT/OUT pin will be driven low.

Note: The IRQ/FT/OUT pin is an open drain which

requires an external pull-up resistor.

Battery Low Warning

The M41ST85Y/W automatically performs battery

voltage monitoring upon power-up and at factory-

programmed time intervals of approximately 24

hours. The Battery Low (BL) Bit, Bit D4 of Flags

is found to be less than approximately 2.5V. The

BL Bit will remain asserted until completion of bat-

tery replacement and subsequent battery low

monitoring tests, either during the next power-up

sequence or the next scheduled 24-hour interval.

If a battery low is generated during a power-up se-

quence, this indicates that the battery is below ap-

proximately 2.5 volts and may not be able to

maintain data integrity in the SRAM. Data should

be considered suspect and verified as correct. A

fresh battery should be installed.

If a battery low indication is generated during the

24-hour interval check, this indicates that the bat-

tery is near end of life. However, data is not com-

promised due to the fact that a nominal VCC is

supplied. In order to insure data integrity during

subsequent periods of battery back-up mode, the

battery should be replaced. The SNAPHAT top

may be replaced while VCC is applied to the de-

vice.

Note: This will cause the clock to lose time during

the interval the SNAPHAT battery/crystal top is

disconnected.

The M41ST85Y/W only monitors the battery when

a nominal VCC is applied to the device. Thus appli-

cations which require extensive durations in the

battery back-up mode should be powered-up peri-

odically (at least once every few months) in order

for this technique to be beneficial. Additionally, if a

battery low is indicated, data integrity should be

verified upon power-up via a checksum or other

technique.

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