M48T201V datasheet(13/33 Pages) STMICROELECTRONICS

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M48T201Y, M48T201V

Data Retention Mode

With valid VCC applied, the M48T201Y/V can be

accessed as described above with READ or

WRITE cycles. Should the supply voltage decay,

the M48T201Y/V will automatically deselect, write

protecting itself (and any external SRAM) when

VCC falls between VPFD (max) and VPFD (min).

This is accomplished by internally inhibiting ac-

cess to the clock registers via the E signal. At this

time, the Reset pin (RST) is driven active and will

remain active until VCC returns to nominal levels.

External RAM access is inhibited in a similar man-

ner by forcing ECON to a high level. This level is

within 0.2V of the VBAT. ECON will remain at this

level as long as VCC remains at an out-of-toler-

ance condition. When VCC falls below the level of

the battery (VBAT), power input is switched from

the VCC pin to the SNAPHAT

® battery and the

clock registers are maintained from the attached

battery supply. External RAM is also powered by

the SNAPHAT battery. All outputs except GCON,

ECON, RST, IRQ/FT and VOUT, become high im-

pedance. The VOUT pin is capable of supplying

100µA of current to the attached memory with less

than 0.3V drop under this condition. On power up,

when VCC returns to a nominal value, write protec-

tion continues for 200ms (max) by inhibiting ECON.

The RST signal also remains active during this

time (see Figure 15., page 27).

Note: Most low power SRAMs on the market to-

day can be used with the M48T201Y/V TIME-

KEEPER® SUPERVISOR. There are, however

some criteria which should be used in making the

final choice of an SRAM to use.

The SRAM must be designed in a way where the

chip enable input disables all other inputs to the

SRAM. This allows inputs to the M48T201Y/V and

SRAMs to be “Don't care” once VCC falls below

VPFD (min). The SRAM should also guarantee

data retention down to VCC = 2.0V. The chip en-

able access time must be sufficient to meet the

system needs with the chip enable (and output en-

able) output propagation delays included.

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