AI01184

13

A0-A12

W

DQ0-DQ7

VCC

M48Z09

M48Z19

G

E2

VSS

8

E1

INT

Figure 1. Logic Diagram

M48Z09

M48Z19

CMOS 8K x 8 ZEROPOWER SRAM

INTEGRATED ULTRA LOW POWER SRAM,

POWER-FAIL CONTROL CIRCUIT and

BATTERY

UNLIMITED WRITE CYCLES

READ CYCLE TIME EQUALS WRITE CYCLE

TIME

AUTOMATIC POWER-FAIL CHIP DESELECT and

WRITE PROTECTION

POWER-FAIL INTERRUPT

CHOICE of TWO WRITE PROTECT

VOLTAGES:

– M48Z09: 4.5V

– M48Z19: 4.2V

SELF CONTAINED BATTERY in the CAPHAT

DIP PACKAGE

11 YEARS of DATA RETENTION in the

ABSENCE of POWER

PIN and FUNCTION COMPATIBLE with the

MK48Z09, 19 and JEDEC STANDARD 8K x 8

SRAMs

DESCRIPTION

non-volatile static RAM which is pin and function

compatible with the MK48Z09,19.

A special 28 pin 600mil DIP CAPHAT

™ package

houses the M48Z09,19 silicon with a long life lith-

ium button cell to form a highly integrated battery

backed-up memory solution.

A0-A12

Address Inputs

DQ0-DQ7

Data Inputs / Outputs

INT

Power Fail Interrupt

E1

Chip Enable 1

E2

Chip Enable 2

G

Output Enable

W

Write Enable

Supply Voltage

Ground

Table 1. Signal Names

28

1

PCDIP28 (PC)

Battery CAPHAT

November 1994

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