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M50FW040 数据表(PDF) 13 Page - STMicroelectronics

部件名 M50FW040
功能描述  4 Mbit 512Kb x8, Uniform Block 3V Supply Firmware Hub Flash Memory
PDF  41 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

M50FW040 数据表(HTML) 13 Page - STMicroelectronics

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M50FW040
Figure 7. FWH Bus Read Waveforms
Table 5. FWH Bus Write Field Definitions
Figure 8. FWH Bus Write Waveforms
Clock
Cycle
Number
Clock
Cycle
Count
Field
FWH0-
FWH3
Memory
I/O
Description
1
1
START
1110b
I
On the rising edge of CLK with FWH4 Low, the contents of
FWH0-FWH3 indicate the start of a FWH Write Cycle.
2
1
IDSEL
XXXX
I
Indicates which FWH Flash Memory is selected. The value
on FWH0-FWH3 is compared to the IDSEL strapping on the
FWH Flash Memory pins to select which FWH Flash
Memory is being addressed.
3-9
7
ADDR
XXXX
I
A 28-bit address phase is transferred starting with the most
significant nibble first.
10
1
MSIZE
0000b
I
Always 0000b (single byte transfer).
11-12
2
DATA
XXXX
I
Data transfer is two cycles, starting with the least significant
nibble.
13
1
TAR
1111b
I
The host drives FWH0-FWH3 to 1111b to indicate a
turnaround cycle.
14
1
TAR
1111b
(float)
O
The FWH Flash Memory takes control of FWH0-FWH3
during this cycle.
15
1
SYNC
0000b
O
The FWH Flash Memory drives FWH0-FWH3 to 0000b,
indicating it has received data or a command.
16
1
TAR
1111b
O
The FWH Flash Memory drives FWH0-FWH3 to 1111b,
indicating a turnaround cycle.
17
1
TAR
1111b
(float)
N/A
The FWH Flash Memory floats its outputs and the host takes
control of FWH0-FWH3.
AI03437
CLK
FWH4
FWH0-FWH3
Number of
clock cycles
START
IDSEL
ADDR
MSIZE
TAR
SYNC
DATA
TAR
11712322
AI03441
CLK
FWH4
FWH0-FWH3
Number of
clock cycles
START
IDSEL
ADDR
MSIZE
DATA
TAR
SYNC
TAR
11712212



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