M50LPW041 datasheet(5/37 Pages) STMICROELECTRONICS

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M50LPW041

To select the Low Pin Count (LPC) Interface the

Interface Configuration pin should be left to float or

driven Low, VIL; to select the Address/Address

Multiplexed (A/A Mux) Interface the pin should be

driven High, VIH. An internal pull-down resistor is

included with a value of RIL; there will be a leakage

current of ILI2 through each pin when pulled to VIH;

see Table 21.

Interface Reset (RP). The Interface Reset (RP)

input is used to reset the memory. When Interface

Reset (RP) is set Low, VIL, the memory is in Reset

mode: the outputs are put to high impedance and

the current consumption is minimized. When RP is

set High, VIH, the memory is in normal operation.

After exiting Reset mode, the memory enters

Read mode.

CPU Reset (INIT). The CPU Reset, INIT, pin is

used to Reset the memory when the CPU is reset.

It behaves identically to Interface Reset, RP, and

the internal Reset line is the logical OR (electrical

AND) of RP and INIT.

Clock (CLK). The Clock, CLK, input is used to

clock the signals in and out of the Input/Output

Communication Pins, LAD0-LAD3. The Clock

conforms to the PCI specification.

Top Block Lock (TBL). The

Top

Block

Lock

input is used to prevent the Top Block (Block 7)

from being changed. When Top Block Lock, TBL,

is set Low, VIL, Program and Block Erase

operations in the Top Block have no effect,

regardless of the state of the Lock Register. When

Top Block Lock, TBL, is set High, VIH, the

protection of the Block is determined by the Lock

not affect the protection of the Main Blocks (Blocks

0 to 6).

Top Block Lock, TBL, must be set prior to a Pro-

gram or Block Erase operation is initiated and

must not be changed until the operation completes

or unpredictable results may occur. Care should

be taken to avoid unpredictable behavior by

changing TBL during Program or Erase Suspend.

Write Protect (WP). The Write Protect input is

used to prevent the Main Blocks (Blocks 0 to 6)

from being changed. When Write Protect, WP, is

set Low, VIL, Program and Block Erase operations

in the Main Blocks have no effect, regardless of

the state of the Lock Register. When Write Protect,

WP, is set High, VIH, the protection of the Block is

determined by the Lock Register. The state of

Write Protect, WP, does not affect the protection of

the Top Block (Block 7).

Write Protect, WP, must be set prior to a Program

or Block Erase operation is initiated and must not

be changed until the operation completes or un-

predictable results may occur. Care should be tak-

en to avoid unpredictable behavior by changing

WP during Program or Erase Suspend.

Reserved for Future Use (RFU). These pins do

not have assigned functions in this revision of the

part. They may be left disconnected or driven Low,

VIL, or High, VIH.

Address/Address Multiplexed (A/A Mux)

Signal Descriptions

For the Address/Address Multiplexed (A/A Mux)

Interface see Figure 2, Logic Diagram, and Table

4, Signal Names.

Address Inputs (A0-A10). The Address Inputs

are used to set the Row Address bits (A0-A10) and

the Column Address bits (A11-A18). They are

latched during any bus operation by the Row/Col-

umn Address Select input, RC.

Data Inputs/Outputs (DQ0-DQ7). The Data In-

puts/Outputs hold the data that is written to or read

from the memory. They output the data stored at

the selected address during a Bus Read opera-

tion. During Bus Write operations they represent

the commands sent to the Command Interface of

the internal state machine. The Data Inputs/Out-

puts, DQ0-DQ7, are latched during a Bus Write

operation.

Output Enable (G). The Output Enable, G, con-

trols the Bus Read operation of the memory.

Write Enable (W). The Write Enable, W, controls

the Bus Write operation of the memory’s Com-

mand Interface.

Row/Column Address Select (RC). The

Row/

Column Address Select input selects whether the

Address Inputs should be latched into the Row

Address bits (A0-A10) or the Column Address bits

(A11-A18). The Row Address bits are latched on

the falling edge of RC whereas the Column

Address bits are latched on the rising edge.

Ready/Busy Output (RB). The Ready/Busy pin

gives the status of the memory’s Program/Erase

Controller. When Ready/Busy is Low, VOL, the

memory is busy with a Program or Erase operation

and it will not accept any additional Program or

Erase

command

except

the

Program/Erase

Suspend command. When Ready/Busy is High,

VOH, the memory is ready for any Read, Program

or Erase operation.

Table 3. System Memory Map

A31:24

A23

Array

Top

FFh

Bottom

00h

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