CLOCK

DATA

300ns (min.)

Figure 3

There must be a complete set of 36 clocks or the

shift registers will not clear.

When power is first applied to the chip an internal

power ON reset signal is generated which resets

all registers and all latches. The START bit and the

first clock return the chip to its normal operation.

Figure 3 shows the timing relationships between

Data, and Clock. A maximum clock frequency of

0.5MHz is assumed.

Figure 4 shows the Output Data Format for the

M5480. Because it uses only 23 of the possible

35 outputs, 12 of the bits are "Don’t Care".

For applications where a lesser number of outputs

are used, it is possible to either increase the current

per output, or operate the part at higher than 1V

The following equation can be used for calcula-

tions.

Figure 4 : Serial Data Bus / Outputs Correspondance

5451

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

START

5480

X

23

22

21

20

19

X

X

18

X

17

16

15

14

13

12

X

START

5451

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

START

5480

X

X

X

11

10

9

8

X

X

X

7

6

5

4

3

2

1

X

START

TYPICAL APPLICATION

23 SEGMENTS

CLOCK

DATA

M5480

DISPLAY DRIVER

VD

VOUT

R

ID

+V C

a)

] (132

where:

°C max)

132

°C/W = thermal coefficient of the package

POWER DISSIPATION OF THE IC

The power dissipation of the IC can be limited using

different configurations.

In this application R must be chosen taking into

account the worst operating conditions.

R is determined by the maximum number of seg-

ments activated.

R

=

M5480

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