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M5481 数据表(PDF) 3 Page - STMicroelectronics

部件名 M5481
功能描述  LED DISPLAY DRIVER
PDF  8 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

M5481 数据表(HTML) 3 Page - STMicroelectronics

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3 - STATIC ELECTRICAL CHARACTERISTICS
(Tamb within operational range, VDD=4.75V to 13.2V, VSS=0V, unless otherwise specified)
Note 1 Output matching is calculated as the percent variation from Imax+Imin/2
Note 2 With a fixed resistor on the brightness input some variation in brightness will occur from one device to another.
Note 3 Absolute maximum for each output should be limited to 40mA.
Note 4 the Vo voltage should be regulated by the user.
4 - FUNCTIONAL DESCRIPTION
The M5481 uses the M5450 die which is packaged
to operate 2-digit alphanumeric displays with mini-
mal interface with the display and the data source.
Serial data transfer from the data source to the dis-
play driver is accomplished with 2 signals, serial
data and clock. using a format of a leading “1” fol-
lowed by the 35 data bits allows data transfer with-
out an additional load signal.
The 35 data bits are latched after the 36th bit is
complete, thus providing non-multiplexed, direct
drive to the display. Outputs change only if the se-
rial data bits differ from the previous time. Display
brightness is determined by control of the output
current for LED displays. A 1nF capacitor should
be connected to brightness control (pin 9) to pre-
vent possible oscillations.
A bloc diagram is shown on Figure 1. The output
current is typically 20 times greater than the cur-
rent into pin 9, which is set by an external variable
resistor.
The latter is an internal limiting resistor of 400
nominal value.
Figure 2 shows the input data format. A start bit of
logical “1” precedes the 35 bits of data. At the 36th
clock a LOAD is generated synchronously with the
high state of the clock, which loads the 35 bits of
the shift registers into the latches.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
VDD
Supply Voltage
4.5
13.2
V
Idd
Supply Current
VDD=13.2V
7
mA
Vi
Input Voltages
Logical “0” Level
Logical “1” Level
+10
µA Input Bias
4.75
≤V
DD≤5.25
VDD>5.25
-0.3
2.2
VDD-
2
0.8
VDD
VDD
V
V
V
IB
Brightness Input Current (Note 2)
0
0.75
mA
VB
Brightness Input Voltage (pin9)
Input Curren=750
µA
Tamb=25°C
3
4.3
V
Vo(off)
Off-state Output Voltage
13.2
V
Io
Output Sink Current (Note 3)
Segment OFF
Segment ON
Vo=3V
Vo=1V (Note 4)
Brightness In.=0
µA
Brightness In.=100
µA
Brightness In.=750
µA
0
2
12
2.7
15
10
10
4
25
µA
µA
mA
mA
fclock
Input Clock Frequency
0
0.5
MHz
Io
Output Matching (Note 1)
±20
%



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