数据搜索系统，热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

预览 PDF HTML

TUSB2136 数据表(PDF) 17 Page - Texas Instruments

部件名 TUSB2136
功能描述  Universal Serial Bus Compound Hub with General Purpose 8052 MCU
PDF  53 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

TUSB2136 数据表(HTML) 17 Page - Texas Instruments

Back Button TUSB2136 Datasheet HTML 13Page - Texas Instruments TUSB2136 Datasheet HTML 14Page - Texas Instruments TUSB2136 Datasheet HTML 15Page - Texas Instruments TUSB2136 Datasheet HTML 16Page - Texas Instruments TUSB2136 Datasheet HTML 17Page - Texas Instruments TUSB2136 Datasheet HTML 18Page - Texas Instruments TUSB2136 Datasheet HTML 19Page - Texas Instruments TUSB2136 Datasheet HTML 20Page - Texas Instruments TUSB2136 Datasheet HTML 21Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 17 / 53 page
background image
2−4
2.2.6
PCON: Power Control Register (at SFR 87h)
7
6
5
4
3
210
SMOD
RSV
RSV
RSV
GF1
GF0
RSV
IDL
R/W
R/O
R/O
R/O
R/W
R/W
R/O
R/W
BIT
NAME
RESET
FUNCTION
0
IDL
0
MCU idle mode bit. This bit can be set by the MCU and is cleared only by the INT1 interrupt.
0
IDL
0
IDL = 0
The MCU is not in idle mode. This bit is cleared by the INT1 interrupt logic when INT1 is
asserted for at least 400
µs.
IDL = 1
The MCU is in idle mode and RAM is in low-power mode. The oscillator/APLL is off and the
WDT is suspended. When in suspend mode, only INT1 can be used to exit from the idle state
and generate an interrupt. INT1 must be asserted for at least 400
µs for the interrupt to be
recognized.
1
RSV
0
Reserved
3−2
GF[1:0]
00
General-purpose bits. The MCU can write and read them.
6−4
RSV
0
Reserved
7
SMOD
0
Double baud-rate control bit. For more information see the UART serial interface in the M8052 core
specification.
2.3
Buffers + I/O RAM Map
The address range from FD80 to FFFF is reserved for data buffers, setup packet, endpoint descriptor blocks (EDB),
and all I/O. RAM space of 512 bytes [FD80−FF7F] is used for EDB and buffers. The FF80−FFFF range is used for
memory-mapped registers (MMR). Table 2−1 represents the internal XDATA space allocation.
Table 2−1. XDATA Space
DESCRIPTION
ADDRESS RANGE
FFFF
Internal
Internal
memory mapped registers
↑
memory mapped registers
(MMR)
↑
memory mapped registers
(MMR)
FF80
FF7F
Endpoint descriptor blocks
Endpoint descriptor blocks
(EDB)
↑
(EDB)
FF08
FF07
Setup packet buffer
↑
Setup packet buffer
FF00
FEFF
512 -Byte
Input endpoint-0 buffer
↑
512 -Byte
RAM
Input endpoint-0 buffer
FEF8
RAM
FEF7
Output endpoint-0 buffer
↑
Output endpoint-0 buffer
FEF0
FEEF
Data buffers
Data buffers
(368 bytes)
↑
Data buffers
(368 bytes)
↑
(368 bytes)
FD80



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com