M54HC112

M74HC112

October 1992

DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

B1R

(Plastic Package)

ORDER CODES :

M54HC112F1R

M74HC112M1R

M74HC112B1R

M74HC112C1R

F1R

(Ceramic Package)

M1R

(Micro Package)

C1R

(Chip Carrier)

PIN CONNECTIONS (top view)

NC =

No Internal

Connection

INPUT AND OUTPUT EQUIVALENT CIRCUIT

DESCRIPTION

.

HIGH SPEED

.

LOW POWER DISSIPATION

.

HIGH NOISE IMMUNITY

.

OUTPUT DRIVE CAPABILITY

10 LSTTL LOADS

.

SYMMETRICAL OUTPUT IMPEDANCE

.

BALANCED PROPAGATION DELAYS

.

WIDE OPERATING VOLTAGE RANGE

.

PIN AND FUNCTION COMPATIBLE

WITH 54/74LS112

The M54/74HC112 is a high speed CMOS DUAL J-K

FLIP-FLOP WITH PRESET AND CLEAR fabricated in

silicon gate C

speed performance of LSTTL combined with true

CMOS

low

power

consumption.

The

M54HC112/M74HC112 dual JK flip-flop features indi-

vidual J,K, clock, and asynchronous set and clear inputs

for each flip-flop. When the clock goes high, the inputs

are enabled and data will be accepted. The logic level

of the J and K inputs may be allowed to change when

the clock pulse is high and the bistable will function as

shown in the truth table. Input data is transferred to the

input on the negative going edge of the clock pulse. All

inputs are equipped withprotection circuits against static

discharge and transient excess voltage.

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