STLC2593

Overview

3/5

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Low power consumption

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Ultra low power architecture with 3 different low-power levels

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Deep Sleep modes, including Host-power saving feature

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Dual Wake-up mechanism: initiated by the Host or by the Bluetooth device

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Communication interfaces

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Fast UART up to 4 MHz

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Flexible SPI interface up to 13 MHz

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PCM interface

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Up to 10 additional flexibly programmable GPIOs

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External interrupts possible through the GPIOs

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Clock support

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System clock input (digital or sine wave) at 9.6, 10, 13, 16, 16.8, 19.2, 26, 33.6 or

38.4 MHz

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Low power clock input at 32.768 kHz

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Memory organization

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On chip RAM, including provision for patches

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On chip ROM, preloaded with SW up to HCI

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Ciphering support up to 128 bits key

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Single power supply with internal regulators for core voltage generation

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Supports 1.65 V to 2.85 V I/O systems

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Auto calibration (VCO, Filters)

1.2

FM radio features

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Worldwide FM band support (76-108 MHz)

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RDS/RBDS processor

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Line-level analog FM output

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2-wire and 3-wire control interface

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2.7 V to 5.5 V supply voltage

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Integrated LDO regulator allows direct connection to battery

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32.768 kHz reference clock

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Frequency synthesizer with integrated VCO

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Digital low-IF receiver

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Signal strength measurement

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Automatic Frequency Control (AFC)

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Automatic Gain Control (AGC)

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Excellent overload immunity

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Adaptive noise suppression