M54HC137

M74HC137

February 1993

3 TO 8 LINE DECODER/LATCH (INVERTING)

B1R

(Plastic Package)

ORDER CODES :

M54HC137F1R

M74HC137M1R

M74HC137B1R

M74HC137C1R

F1R

(Ceramic Package)

M1R

(Micro Package)

C1R

(Chip Carrier)

PIN CONNECTIONS (top view)

NC =

No Internal

Connection

INPUT AND OUTPUT EQUIVALENT CIRCUIT

DESCRIPTION

.

HIGH SPEED

.

LOW POWER DISSIPATION

.

HIGH NOISE IMMUNITY

.

OUTPUT DRIVE CAPABILITY

10 LSTTL LOADS

.

SYMMETRICAL OUTPUT IMPEDANCE

.

BALANCED PROPAGATION DELAYS

.

WIDE OPERATING VOLTAGE RANGE

.

PIN AND FUNCTION COMPATIBLE

WITH 54/74LS137

The M54/74HC137 is a high speed CMOS 3 TO 8LINE

DECODER/LATCH (INVERTING) fabricated in silicon

gate C

performance of LSTTL combined with true CMOS low

power consumption. This device is a 3 to 8line decoder

withlatches on thethree address inputs. When GL goes

from low tohigh, theaddress present at theselect inputs

(A, B and C) is stored in the latches. AslongasGL re-

mains high no address changes will be recognized. Out-

put enable pins G1 and G2, control the state of the

outputs independently of the select or latch-enable in-

puts. All the outputs are high unless G1 is high and G2

is low. The HC137 is ideally suited for the implementa-

tion of glitch-free decoders in stored-address applica-

tions in bus oriented systems. All inputs are equipped

withprotection circuits against staticdischarge and tran-

sient excess voltage.

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