M54HC138

M74HC138

October 1992

3 TO 8 LINE DECODER (INVERTING)

B1R

(Plastic Package)

F1R

(Ceramic Package)

M1R

(Micro Package)

C1R

(Chip Carrier)

PIN CONNECTIONS (top view)

NC =

No Internal

Connection

INPUT AND OUTPUT EQUIVALENT CIRCUIT

ORDER CODES :

M54HC138F1R

M74HC138M1R

M74HC138B1R

M74HC138C1R

DESCRIPTION

.

HIGH SPEED

.

LOW POWER DISSIPATION

.

OUTPUT DRIVE CAPABILITY

10 LSTTL LOADS

.

BALANCED PROPAGATION DELAYS

.

SYMMETRICAL OUTPUT IMPEDANCE

.

HIGH NOISE IMMUNITY

.

WIDE OPERATING VOLTAGE RANGE

.

PIN AND FUNCTION COMPATIBLE

WITH 54/74LS138

The M54/74HC138 is a high speed CMOS 3 TO 8

LINE DECODER fabricated in silicon gate C

technology.

It has the same high speed performance of LSTTL

combined with true CMOS low power consumption.

If the device is enabled, 3 binary select inputs (A, B

and C) determine which one of the outputs will go

low. If enable input G1 is held low or either G2A or

G2B is held high, the decoding function is inhibited

and all the 8 outputs go high.

Three enable inputs are provided to ease cascade

connection and application of address decoders for

memory systems. All inputs are equipped with pro-

tection circuits against static discharge and tran-

sient excess voltage.

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