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AM261...ZNC 数据表(PDF) 159 Page - Texas Instruments |
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AM261...ZNC 数据表(HTML) 159 Page - Texas Instruments |
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159 / 218 page  tO9t tO8t tO7t tO11t O12 O10 OSPI_CSn OSPI_CLK OSPI_D[i:0] Figure 6-53. OSPI Switching Characteristics – PHY SDR 6.11.5.13.2.2.2 OSPI0 PHY DDR Timing 6.11.5.13.2.2.2.1 OSPI0 DLL Delay Mapping for PHY DDR Timing Modes MODE OSPI_PHY_CONFIGURATION_REG BIT FIELD DELAY VALUE Transmit 1.8V PHY_CONFIG_TX_DLL_DELAY_FLD 0x1E 3.3V PHY_CONFIG_TX_DLL_DELAY_FLD 0x1E Receive 1.8V, DQS PHY_CONFIG_RX_DLL_DELAY_FLD 0x14 3.3V, DQS PHY_CONFIG_RX_DLL_DELAY_FLD 0x19 1.8V, DDR with External Board Loopback PHY_CONFIG_RX_DLL_DELAY_FLD 0x64 3.3V, DDR with External Board Loopback PHY_CONFIG_RX_DLL_DELAY_FLD 0x69 6.11.5.13.2.2.2.2 OSPI0 Timing Requirements - PHY DDR Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT O15 tsu(D-LBCLK) Setup time, OSPI_D[7:0] valid before active OSPI_DQS edge 1.8V, DDR with DQS 0.400 ns 3.3V, DDR with DQS 0.800 ns 1.8V, DDR with External Board Loopback 6 ns 3.3V, DDR with External Board Loopback 7 ns O16 th(LBTCLK-D) Hold time, OSPI_D[7:0] valid after active OSPI_DQS edge 1.8V, DDR with DQS 0.500 ns 3.3V, DDR with DQS 0.400 ns 1.8V, DDR with External Board Loopback 0 ns 3.3V, DDR with External Board Loopback 0 ns www.ti.com AM2612, AM2611, AM2611-Q1, AM2612-Q1 SPRSPA7C – SEPTEMBER 2024 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 159 Product Folder Links: AM2612 AM2611 AM2611-Q1 AM2612-Q1 |
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