AM261...ZNC datasheet(70/218 Pages) TI2

70 / 218 page

Table 5-42. OSPI0 Signal Descriptions (continued)

Signal Name [1]

Type

[2]

Description [3]

ZCZ PIN [4]

ZFG PIN [4]

ZEJ PIN [4]

ZNC PIN [4]

OSPI0_CSn0

OSPI0 Chip Select 0

H1, J2, P1

J3, L2, U4

F3, N3

G1, R1

OSPI0_CSn1

OSPI0 Chip Select 1

F4, R3

G2, T2

D2, M3

D2, R2

OSPI0_D0

OSPI0 Data bit 0

G3, N1, N2,

H2, M3, R2,

E2, L2, M2,

E1, M2, N2,

OSPI0_D1

OSPI0 Data bit 1

F1, J1, K3,

G1, K2, M2,

D1, G1, G3,

D1, J1, N1

OSPI0_D2

OSPI0 Data bit 2

L1, M1, M4

P1, P2, T1

J3, K1, L3

K2, L1, P2

OSPI0_D3

OSPI0 Data bit 3

K4, P3

L1, U1

H2, N2

H2, P1

OSPI0_D4

OSPI0 Data bit 4

M1, M3, P3

P1, R4, U1

J3, L1, N2

K2, M1, P1

OSPI0_D5

OSPI0 Data bit 5

K2, L1

K1, P2

G2, K1

G2, L1

OSPI0_D6

OSPI0 Data bit 6

L1, L2, M4

N2, P2, T1

K1, K2, L3

J2, L1, P2

OSPI0_D7

OSPI0 Data bit 7

J4, K1

L4, N1

H3, J2

H1, K1

OSPI0_RESET_OUT0(2) (3)

OSPI0 Reset Out 0

B9, D9, G1,

G2, J1, J3

B11, C9, E1,

J1, K2, K4

C11, D3, D8,

F2, G3

B10, C1, F2

OSPI0_RESET_OUT1

OSPI0 Reset Out 1

A9, B8, H1

A11, B10, J3

B8, C10

A10, A11

(1)

OSPI0_LBCLKO is a clock loopback output signal used for peripheral timing.

(2)

In OSPI boot mode, the AM261x ROM code configures GPIO61 as OSPI0_RESET_OUT0 and drives the pin low to reset an external

OSPI device during this boot mode. However, due to a configuration in the OSPI controller, this pin does not de-assert after and

external OSPI flash device resets, thus holding any external flash device in reset and causing the boot to fail. For more information,

see the AM261x Errata Document.

(3)

For additional information on OSPI flash reset, see OSPI Reset within the Applications, Implementation and Layout section.

Table 5-43. OSPI1 Signal Descriptions

Signal Name [1]

Type

[2]

Description [3]

ZCZ PIN [4]

ZFG PIN [4]

ZEJ PIN [4]

ZNC PIN [4]

OSPI1_CLK

OSPI1 Clock

H2, K1, R17

H1, N1, W20

E1, J2, P16

F1, K1, V19

OSPI1_DQS

OSPI1 Data Strobe (DQS) or

Loopback Clock input

P18

U19

L13

R17

OSPI1_ECC_FAIL

OSPI1 ECC Failure Status Pin

A9, M2, N17

A11, M1, T19 C10, H1, M15 A11, J3, T18

OSPI1_LBCLKO (1)

OSPI1 Loopback Clock output

OSPI1_CSn0

OSPI1 Chip Select 0

J2, P17

L2, V20

F3, N16

G1, U19

OSPI1_CSn1

OSPI1 Chip Select 1

OSPI1_D0

OSPI1 Data bit 0

G3, N2, R18

H2, M3, V19

E2, L2, M14

E1, M2, U17

OSPI1_D1

OSPI1 Data bit 1

F1, K3, U17

G1, M2, Y18

D1, G1, P14

D1, J1, W17

OSPI1_D2

OSPI1 Data bit 2

T17

W18

P15

V17

OSPI1_D3

OSPI1 Data bit 3

U18

Y19

R16

W18

OSPI1_D4

OSPI1 Data bit 4

T18

W19

N14

V18

OSPI1_D5

OSPI1 Data bit 5

N18

U20

L15

R18

OSPI1_D6

OSPI1 Data bit 6

M18

T20

M16

T19

OSPI1_D7

OSPI1 Data bit 7

P16

V18

N15

U18

OSPI1_RESET_OUT0

OSPI1 Reset Out 0

B9, G1, N16

B11, K4, R17

D8, F2, L16

B10, F2, P18

OSPI1_RESET_OUT1

OSPI1 Reset Out 1

B10

A10

(1)

OSPI1_LBCLKO is a clock loopback output signal used for peripheral timing.

AM2612, AM2611, AM2611-Q1, AM2612-Q1

SPRSPA7C – SEPTEMBER 2024 – REVISED JULY 2025

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