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AM261...ZEJQ1 数据表(PDF) 157 Page - Texas Instruments |
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AM261...ZEJQ1 数据表(HTML) 157 Page - Texas Instruments |
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157 / 218 page  (6) Minimum and maximum delay times for OSPI_D[7:0] outputs are not defined when Data Training is used to find the optimum data valid window. tO4t tO3t tO5t tO2t tO1t O6 O6 OSPI_CSn OSPI_CLK OSPI_D[i:0] Figure 6-50. OSPI Switching Characteristics – PHY DDR Data Training 6.11.5.13.2.2 OSPI0 Without Data Training Note Timing parameters defined in this section are only applicable for the OSPI0 interface when data training is not implemented and DLL delays are configured as described in OSPI0 DLL Delay Mapping for PHY SDR Timing Modes and OSPI0 DLL Delay Mapping for PHY DDR Timing Modes. 6.11.5.13.2.2.1 OSPI0 PHY SDR Timing 6.11.5.13.2.2.1.1 OSPI0 DLL Delay Mapping for PHY SDR Timing Modes MODE OSPI_PHY_CONFIGURATION_REG BIT FIELD DELAY VALUE Transmit 1.8V PHY_CONFIG_TX_DLL_DELAY_FLD 0x23 3.3V PHY_CONFIG_TX_DLL_DELAY_FLD 0x2F Receive 1.8V, Internal PHY Loopback PHY_CONFIG_RX_DLL_DELAY_FLD 0x3C 3.3V, Internal PHY Loopback PHY_CONFIG_RX_DLL_DELAY_FLD 0x32 1.8V, External Board Loopback PHY_CONFIG_RX_DLL_DELAY_FLD 0x0 3.3V, External Board Loopback PHY_CONFIG_RX_DLL_DELAY_FLD 0x0 6.11.5.13.2.2.1.2 OSPI0 Timing Requirements - PHY SDR Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT O19 tsu(D-CLK) Setup time, OSPI_D[7:0] valid before active OSPI_CLK edge 1.8V, SDR with Internal PHY Loopback 6 ns 3.3V, SDR with Internal PHY Loopback 7 ns O20 th(CLK-D) Hold time, OSPI_D[7:0] valid after active OSPI_CLK edge 1.8V, SDR with Internal PHY Loopback 0.25 ns 3.3V, SDR with Internal PHY Loopback 0 ns www.ti.com AM2612, AM2611, AM2611-Q1, AM2612-Q1 SPRSPA7C – SEPTEMBER 2024 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 157 Product Folder Links: AM2612 AM2611 AM2611-Q1 AM2612-Q1 |
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