AM261...ZEJQ1 datasheet(2/218 Pages) TI2

2 / 218 page

General Connectivity:

• 6x Universal Asynchronous RX-TX (UART)

• 4x Serial Peripheral Interface (SPI) controllers

• 3x Local Interconnect Network (LIN) ports

• 3x Inter-Integrated Circuit (I2C) ports

• 2x Modular Controller Area Network (MCAN)

modules with CAN-FD support

• 1x Fast Serial Interface Transmitter (FSITX)

• 1x Fast Serial Interface Receiver (FSIRX)

• Up to 141x General Purpose I/O (GPIO) pins

Sensing and Actuation:

• Real-time Control Subsystem (CONTROLSS)

• Flexible Input/Output Crossbars (XBAR)

• 3x 12-bit Analog to Digital Converters (ADC) with 3

MSPS maximum sampling rate

– Each ADC module with

• 7x Single ended channels OR

• 3x Differential channels

– Highly configurable ADC digital logic

• With selectable internal or external

reference

• 4x Post-Processing blocks for each ADC

module

• 9x Analog Comparators with internal 12-bit DAC

reference (CMPSSA)

• 1x 12 bit Digital to Analog Converter (DAC)

• 10x Enhanced High Resolution Pulse Width

Modulation (eHRPWM) modules

– Single or Dual PWM channels

– Advanced PWM Configurations

– Enhanced HRPWM time resolution

• 8x Enhanced Capture (ECAP) modules

• 2x Enhanced Quadrature Encoder Pulse (EQEP)

modules

• 2x Sigma-Delta Filter Modules (SDFM)

Data Storage

• 1 × 4-bit Multi-Media Card/Secure Digital

(MMC/SD) interface

Security:

• Hardware Security Module (HSM) with support for

Auto SHE 1.1/EVITA

• Targeted for ISO 21434 compliance

• Secure boot support

– Device Take Over Protection

– Hardware enforced root-of-trust

– Authenticated boot

– SW Anti-rollback protection

• Debug security

– Secure device debug only after proper

authentication

– Ability to disable device debug functionality

• Device ID and Key Management

– Support for OTP Memory (FUSEROM)

• Store root keys and other security fields

– Separate EFUSE controllers and FUSE ROMs

– Unique Device Public Identifiers

• Memory Protection Units (MPU)

– Dedicated Arm® MPU per Cortex®-R5F core

– System MPU - present at various interfaces in

the SoC (MPU or Firewall)

– 8 to 16 Programmable Regions

• Enable/Privilege ID

• Start/End Address

• Read/Write/Cachable

• Secure/Non-Secure

• Cryptographic acceleration

– Cryptographic cores with DMA Support

– AES - 128/192/256-bit key sizes

– SHA2 - 256/384/512-bit support

– DRBG with pseudo and true random number

generator

AM2612, AM2611, AM2611-Q1, AM2612-Q1

SPRSPA7C – SEPTEMBER 2024 – REVISED JULY 2025

www.ti.com

Submit Document Feedback

Product Folder Links: AM2612 AM2611 AM2611-Q1 AM2612-Q1

AM261...ZEJQ1 数据表(PDF) 2 Page - Texas Instruments

AM261...ZEJQ1 数据表(HTML) 2 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载