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AM261...ZEJQ1 数据表(PDF) 114 Page - Texas Instruments |
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AM261...ZEJQ1 数据表(HTML) 114 Page - Texas Instruments |
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114 / 218 page  6.11.5.1.3 CPSW RMII Timing 6.11.5.1.3.1 CPSW RMII Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input Slew Rate VDD = 3.3V 0.4 1.2 V/ns OUTPUT CONDITIONS CL Output Load Capacitance 3 25 pF 6.11.5.1.3.2 CPSW RMII[x]_REFCLK Timing Requirements - RMII Mode NO. PARAMETER DESCRIPTION MIN MAX UNIT RMII1 tc(REF_CLK) Cycle time, REF_CLK 19.999 20 ns RMII2 tw(REF_CLKH) Pulse duration, REF_CLK High 7 13 ns RMII3 tw(REF_CLKL) Pulse duration, REF_CLK Low 7 13 ns RMII[x]_REF_CLK RMII2 RMII3 RMII1 Figure 6-13. CPSW RMII[x]_REF_CLK Timing Requirements – RMII Mode 6.11.5.1.3.3 CPSW RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER Timing Requirements - RMII Mode NO. PARAMETER DESCRIPTION MIN MAX UNIT RMII4 tsu(RXD-REF_CLK) Setup time, RXD[1:0] valid before REF_CLK 4 ns tsu(CRS_DV-REF_CLK) Setup time, CRS_DV valid before REF_CLK 4 ns tsu(RX_ER-REF_CLK) Setup time, RX_ER valid before REF_CLK 4 ns RMII5 th(REF_CLK-RXD) Hold time, RXD[1:0] valid after REF_CLK 2 ns th(REF_CLK-CRS_DV) Hold time, CRS_DV valid after REF_CLK 2 ns th(REF_CLK-RX_ER) Hold time, RX_ER valid after REF_CLK 2 ns RMII4 RMII5 RMII[x]_ _ REF CLK RMII[x]_RXD[1:0], RMII[x]_CRS_DV, RMII[x]_RX_ER Figure 6-14. CPSW RMII[x]_RXD[1:0], RMII[x]_CRS_DV, RMII[x]_RX_ER Timing Requirements – RMII Mode AM2612, AM2611, AM2611-Q1, AM2612-Q1 SPRSPA7C – SEPTEMBER 2024 – REVISED JULY 2025 www.ti.com 114 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: AM2612 AM2611 AM2611-Q1 AM2612-Q1 |
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