M54HC237

M74HC237

October 1992

3 TO 8 LINE DECODER LATCH

B1R

(Plastic Package)

ORDER CODES :

M54HC237F1R

M74HC237M1R

M74HC237B1R

M74HC237C1R

F1R

(Ceramic Package)

M1R

(Micro Package)

C1R

(Chip Carrier)

PIN CONNECTIONS (top view)

NC =

No Internal

Connection

.

HIGH SPEED

.

LOW POWER DISSIPATION

.

HIGH NOISE IMMUNITY

.

OUTPUT DRIVE CAPABILITY

10 LSTTL LOADS

.

SYMMETRICAL OUTPUT IMPEDANCE

.

BALANCED PROPAGATION DELAYS

.

WIDE OPERATING VOLTAGE RANGE

.

PIN AND FUNCTION COMPATIBLE

WITH 54/74LS237

The M54/74HC237 is a high speed CMOS 3 TO 8

LINE DECODER LATCH fabricated in silicon gate

C

It has the same high speed performance of LSTTL

combined with true CMOS low power consumption.

When GL goes from low to high, the address present

at the select inputs (A, B, C) is stored in the latches.

As long as GL remains high no address changes will

be recognized. Output enable controls, G1 and G2

control the state of the outputs independantly of the

select or latch-enable inputs. All of the outputs are low

unless G1 is high and G2 is low. The ’HC237 is ideally

suited for the implementation of glitch-free decoders

in stored-address applications in bus oriented sys-

tems. All inputs are equipped with protection circuits

against static discharge and transient excess voltage.

DESCRIPTION

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