M54HC280

M74HC280

October 1992

9 BIT PARITY GENERATOR

B1R

(Plastic Package)

ORDER CODES :

M54HC280F1R

M74HC280M1R

M74HC280B1R

M74HC280C1R

F1R

(Ceramic Package)

M1R

(Micro Package)

C1R

(Chip Carrier)

PIN CONNECTIONS (top view)

NC =

No Internal

Connection

.

HIGH SPEED

.

LOW POWER DISSIPATION

.

HIGH NOISE IMMUNITY

.

OUTPUT DRIVE CAPABILITY

10 LSTTL LOADS

.

SYMMETRICAL OUTPUT IMPEDANCE

.

BALANCED PROPAGATION DELAYS

.

WIDE OPERATING VOLTAGE RANGE

.

PIN AND FUNCTION COMPATIBLE WITH

54/74LS280

The M54/74HC280 is a high speed CMOS 9-BIT

PARITY GENERATOR fabricated in silicon gate

C

formance of LSTTL combined with true CMOS low

consumption.

It is composed of nine data inputs (A to I) and

odd/even parity outputs (

Σ ODD and Σ EVEN). The

nine data inputs control the output conditions. When

the number of high level inputs is odd,

ΣODD output

is kept high and

ΣEVEN output low. Conversely,

when the number is even ,

ΣEVEN output is kept

high and

ΣODD low.

This IC generates either odd or even parity making

it flexible application.

The word-length capability is easily expanded by

cascading.

All inputs are equipped with protection circuits

against static discharge and transient excess volt-

age.

DESCRIPTION

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