STPM11_08 datasheet(30/45 Pages) STMICROELECTRONICS

30 / 45 page

Theory of operation

STPM11/12/13/14

30/45

The mode signals bit can be written using the normal writing procedure of the CFGI

interface (see CFGI par. 7.17)

– RD mode signal has been already described in par. 7.15 (configuring the STPM1x),

but there is another implied function of the signal RD. When it is set, each sense

amplifier is disconnected from corresponding anti-fuse element and this way, its 3V

NMOS gate is protected from the high voltage of VOTP during permanent write

operation. This means that as long as the VOTP voltage reads more than 3V, the

signal RD should be set.

– PUMP. When set, the PUMP mode signal transforms the MOP and MON pins to act

as driving signals to implement a charge-pump DC-DC converter (see Figure 23).

This feature is useful in order to boost the VCC supply voltage of the STPM1x to

generate the VOTP voltage (14 V to 20 V) needed to program the OTP anti-fuse

elements.

– WE (write Enable): This mode signal is used to permanently write to the OTP anti-

fuse element. When this bit is not set, any writing to the configuration bit is recorded

in the shadow latches. When this bit is set, the writing is recorded both in the shadow

latch and in the OTP anti-fuse element.

7.17

CFGI: Configuration interface

The CFGI interface supports a simple serial protocol, which is implemented in order to

enable the configuration of STPM1x which allows writing the Mode bits and the

configuration bits (temporarily or permanently);

Four pins of the device are dedicated to this purpose: SCS, SYN-NP, SCLNCN, SDATD.

SCS, SYN-NP, SCL-NLC and SDATD are all input pins. A high level signal for these pins

means a voltage level higher than 0.75xVCC, while a low level signal means a voltage value

lower than 0.25xVCC.

The condition in which SCS, SYN-NP and SCL-NLC inputs are set to high level determines

the idle state of the CFGI interface and no data transfer occurs.

– SCS: in the STPM1X, the SYN-NP, SCL-NLC and SDA-TD have the dual task to

provide information on the meter status (see Pin Description table) and to allow CFGI

communication. The SCS pin allows using the above pins for CFGI communication

when it is low and allows the normal operation of SYN-NP, SCL-NLC and SDA-TD

Table 15.

Mode signals description

Signal

Name

Bit

Value

Status

Binary

Command

Hex

Command

PUMP

MOP and MON operate normally

0111000x

70 or 71

MOP and MON provide the driving signals to implement a

charge-pump DC-DC converter

1111000x

F0 or F1

The 56 Configuration bits originated by OTP anti-fuses

0111101x

7A or 7B

The 56 Configuration bits originated by shadow latches

1111101x

FA or FB

Any writing in the configuration bits is recorded in the shadow

latches

0111110x

7C or 7D

Any writing in the configuration bits is recorded both in the

shadow latches and in the OTP anti-fuse elements

1111110x

FC or FD

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