数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

M54HC40102 数据表(PDF) 7 Page - STMicroelectronics

部件名 M54HC40102
功能描述  8 STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS
PDF  14 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

M54HC40102 数据表(HTML) 7 Page - STMicroelectronics

Back Button M54HC40102 Datasheet HTML 3Page - STMicroelectronics M54HC40102 Datasheet HTML 4Page - STMicroelectronics M54HC40102 Datasheet HTML 5Page - STMicroelectronics M54HC40102 Datasheet HTML 6Page - STMicroelectronics M54HC40102 Datasheet HTML 7Page - STMicroelectronics M54HC40102 Datasheet HTML 8Page - STMicroelectronics M54HC40102 Datasheet HTML 9Page - STMicroelectronics M54HC40102 Datasheet HTML 10Page - STMicroelectronics M54HC40102 Datasheet HTML 11Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 7 / 14 page
background image
The HC40102 and HC40103 are 8-stage preset-
table synchronous down counters. Carry Out/Zero
Detect (CO/ZD) is output at the ”L” level for the
period of 1 bit when the readout becomes ”0”. The
HC40102 adopts binary coded decimal notation,
making setting up to 99 counts possible. While the
HC40103 adopts 8-bit binary counter and can set up
to 255 counts.
COUNT OPERATION
At the ”H” level of control input of CLEAR, SPE and
APE, the counter carriers out down count operation
one by one at the rise of pulse given to CLOCK input.
Count operation can be inhibited by setting Carry
Input/Clock Enable CI/CE to the ”H” level.
CO/ZD is output at the ”L” level when the readout
becomes ”0” but is not output even if the readout
becomes ”0” when CI/CE is at the ”H” level, thus
maintaining the ”H” level.
Synchronous cascade operation can be carried out
by using CI/CE input and CO/ZD output.
The contents of count jump to maximum count (99
for the HC40102 and 225 for the HC40103) if clock
is given when the readout is ”0”. Therefore, oper-
ation of 100-frequency division and that of 256-fre-
quency division are carried out for the HC40102 and
HC40103, respectively, when clock input alone is
given without various kinds of preset operation.
PRESET OPERATION AND RESET OPERATION
When Clear (CLEAR) input is set to the ”L” level, the
readout is set to the maximum count independetly
of other inputs. When Asynchronous Preset Enable
(APE) input is set to the ”L” level, readouts given on
J0 to J7 can be preset asynchronously to counter in-
dependently of inputs other than CLEAR input.
When Synchronous Preset Enable (SPE) is set to
the ”L” level, the readouts given on J0 to J7 can be
preset to counter synchronously with the rise of
clock.
As to these operation modes, refer to the truth table.
FUNCTIONAL DESCRIPTION
Input
Output
CLEAR APE S P E J
T E CLO CK
Q n +1
LX
X
X
X
X
L
HL
X
L
X
X
L
HL
X
H
X
X
H
HH
L
L
X
_
v
_L
HH
L
H
X
_
v
_H
HH
L
X
X
_
w
_
__
Q n
HH
H
X
L
_
v
_Qn
HH
H
X
H
X
__
Q n
M54/M74HC40102/40103
7/14



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com