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AM261...ZEJ 数据表(PDF) 121 Page - Texas Instruments |
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AM261...ZEJ 数据表(HTML) 121 Page - Texas Instruments |
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121 / 218 page  6.11.5.5 Fast Serial Interface (FSI) Note The device has multiple FSI modules. FSIn is a generic prefix applied to FSI signal names, where n represents the specific FSI module. For more information, see Fast Serial Interface section in the device TRM. 6.11.5.5.1 FSI Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input Slew Rate 0.8 4 V/ns OUTPUT CONDITIONS CL Output Load Capacitance 1 7 pF 6.11.5.5.2 FSIRX Timing Requirements NO. PARAMETER DESCRIPTION MIN MAX UNIT FSIR1 tc(RX_CLK) Cycle time, FSIRXn_CLK 16.67 ns FSIR2 tw(RX_CLK) Pulse width, FSIRXn_CLK low or FSIRXn_CLK high 0.35P(1) – 1 0.65P(1) + 1 ns FSIR3 tsu(RX_D–RX_CLK) Setup time, FSIRXn_D[0:1] valid before FSIRXn_CLK 1.7 ns FSIR4 th(RX_CLK–RX_D) Hold time with respect to both edges of FSIRXn_CLK 2 ns (1) P = Tc(RXCLK) = RX Interface clock period in ns. FSI_RXn_CLK FSIR2 FSIR1 FSIR3 FSI_RXn_D0 FSI_RXn_D1 FSIR4 FSIR2 Figure 6-23. FSI Timing Requirements 6.11.5.5.3 FSIRX Switching Characteristics NO. PARAMETER DESCRIPTION MIN MAX UNIT FSIR5 td(RX_CLK) FSIRXn_CLK delay compensation at RX_DLYLINE_CTRL[RXCLK_DLY]=31 10 30 ns FSIR6 td(RX_D0) FSIRXn_D0 delay compensation at RX_DLYLINE_CTRL[RXCLK_DLY]=31 10 30 ns FSIR7 td(RX_D1) FSIRXn_D1 delay compensation at RX_DLYLINE_CTRL[RXCLK_DLY]=31 10 30 ns FSIR8 td(DELAY_ELEMENT) Incremental delay of each delay line element for FSIRXn_CLK, FSIRXn_D0, and FSIRXn_D1 0.3 1 ns www.ti.com AM2612, AM2611, AM2611-Q1, AM2612-Q1 SPRSPA7C – SEPTEMBER 2024 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 121 Product Folder Links: AM2612 AM2611 AM2611-Q1 AM2612-Q1 |
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