 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
AM261...ZEJ 数据表(PDF) 126 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
AM261...ZEJ 数据表(HTML) 126 Page - Texas Instruments |
|
|
126 / 218 page  6.11.5.7.3 GPMC/NOR Flash Switching Characteristics - Synchronous Mode 100MHz (18) (19) (20) NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT F0 tc(clk) Clock period, GPMC0_CLK, GPMC0_FCLK_MUX 10(21) ns F1 tw(clk) Typical pulse duration, GPMC0_CLK high or low 0.475P(16) – 0.3(21) ns F2 td(clkH-csnV) Delay time, GPMC0_CLK rising edge to GPMC0_CSn[x](15) transition F(6) – 2.2(21) F(6)+3.75 ns F3 td(clkH-csnIV) Delay time, GPMC0_CLK rising edge to GPMC0_CSn[x](15) invalid E(5) – 2.2 E(5)+3.18 ns F4 td(aV-clk) Delay time, GPMC0_A[27:1] valid to GPMC0_CLK first edge B(2) – 2.3(21) B(2) + 4.5 ns F5 td(clkH-aIV) Delay time, GPMC0_CLK rising edge to GPMC0_A[27:1] invalid –2.3(21) 4.5 ns F6 td(be[x]nV-clk) Delay time, GPMC0_BE0n_CLE, GPMC0_BE1n valid to GPMC0_CLK first edge B(2) – 2.3(21) B(2) + 1.9 ns F7 td(clkH-be[x]nIV) Delay time, GPMC0_CLK rising edge to GPMC0_BE0n_CLE, GPMC0_BE1n invalid(12) D(4) – 2.3(21) D(4) + 1.9 ns F7 td(clkL-be[x]nIV) Delay time, GPMC0_CLK falling edge to GPMC0_BE0n_CLE, GPMC0_BE1n invalid(13) D(4) – 2.3(21) D(4) + 1.9 ns F7 td(clkL-be[x]nIV) Delay time, GPMC0_CLK falling edge to GPMC0_BE0n_CLE, GPMC0_BE1n invalid(14) D(4) – 2.3(21) D(4) + 1.9 ns F8 td(clkH-advn) Delay time, GPMC0_CLK rising edge to GPMC0_ADVn_ALE transition G(7) (8) – 2.3(21) G(7) (8) + 4.5 ns F9 td(clkH-advnIV) Delay time, GPMC0_CLK rising edge to GPMC0_ADVn_ALE invalid D(4) – 2.3(21) D(4) + 4.5 ns F10 td(clkH-oen) Delay time, GPMC0_CLK rising edge to GPMC0_OEn_REn transition H(9) – 2.3(21) H(9) + 3.5 ns F11 td(clkH-oenIV) Delay time, GPMC0_CLK rising edge to GPMC0_OEn_REn invalid H(9) – 2.3(21) H(9) + 3.5 ns F14 td(clkH-wen) Delay time, GPMC0_CLK rising edge to GPMC0_WEn transition I(10) – 2.3(21) I(10) + 4.5 ns F15 td(clkH-do) Delay time, GPMC0_CLK rising edge to GPMC0_AD[31:0] transition(12) J(11) – 2.3(21) J(11) + 2.7 ns F15 td(clkL-do) Delay time, GPMC0_CLK falling edge to GPMC0_AD[31:0] data bus transition(13) J(11) – 2.3(21) J(11) + 2.7 ns F15 td(clkL-do) Delay time, GPMC0_CLK falling edge to GPMC0_AD[31:0] data bus transition(14) J(11) – 2.3(21) J(11) + 2.7 ns F17 td(clkH-be[x]n) Delay time, GPMC0_CLK rising edge to GPMC0_BE0n_CLE transition(12) J(11) – 2.3(21) J(11) + 1.9 ns F17 td(clkL-be[x]n) Delay time, GPMC0_CLK falling edge to GPMC0_BE0n_CLE, GPMC0_BE1n transition(13) J(11) – 2.3(21) J(11) + 1.9 ns F17 td(clkL-be[x]n) Delay time, GPMC0_CLK falling edge to GPMC0_BE0n_CLE, GPMC0_BE1n transition(14) J(11) – 2.3(21) J(11) + 1.9 ns F18 tw(csnV) Pulse duration, GPMC0_CSn[x](15) low Read A(1) ns Write A(1) ns F19 tw(be[x]nV) Pulse duration, GPMC0_BE0n_CLE, GPMC0_BE1n low Read C(3) ns Write C(3) ns AM2612, AM2611, AM2611-Q1, AM2612-Q1 SPRSPA7C – SEPTEMBER 2024 – REVISED JULY 2025 www.ti.com 126 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: AM2612 AM2611 AM2611-Q1 AM2612-Q1 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
