AM261...ZCZQ1 datasheet(103/218 Pages) TI2

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6.11.2 Power Supply Sequencing

This section describes power supply sequencing required to ensure proper device operation.

Note

Please note that depending on the speed grade of the device, the VDD core voltage supply is

different. This section uses the 1.2V/1.25V notation to reference this difference. For your specific

device, please reference Recommended Operating Connections and Operating Performance Points

for more information.

6.11.2.1 Power-On and Reset Sequencing

As with previous AM26x devices, AM261x has no sequencing requirement with respect to the primary core

digital VDD 1.2V/1.25V and I/O power 3.3V rails. There are two on-die LDO that are supplied through the

VDDS33 and VDDA33 power nets respectively. These on-die LDO generate the required VDDS1V8 and

VDDA1V8 1.8V digital and analog power. The AM261x does require the minimum ramp time be respected

for 3.3V power-on. Additional PORz and SOP boot mode latch timing must be respected by the EVM design as

well. Power-On Sequencing describes the device power-on sequencing.

Table 6-2. AM261x Power-On Sequencing

PARAMETER

MIN

MAX

UNIT

tRAMP_3V3

Minimal ramp time for the 3.3V digital VDDSHV_x power nets. Measured from GND to

VDDSHV_x 3,.V nominal

100

–

μs

tRAMP_1V8

Minimal ramp time for the 1.8V digital VDDSHV_x power nets. Measured from GND to

VDDSHV_x 1.8V nominal.

100

–

μs

tRAMP_1V2

Minimal ramp time for the 1.2V/1.25V core digital VDD and power nets. Measured from

GND to VDD 1.2V/1.25V nominal.

100

–

μs

tDELAY_3V3

Minimal delay between when the VDDSHV_x 3.3V power is at nominal voltage until the

VDDSHV_x 1.8V and VDD 1.2V/1.25V nets are enabled.

(1)

–

μs

tDELAY_PG

Minimal time between when VDDSHV_x 3.3V, VDDSHV_x 1.8V and VDD 1.2V/1.25V

rails are all detected valid at nominal voltage before PORz signal can be transitioned

from low to high voltage.

–

μs

tSOP_Sampled

Time from PORz de-assertion until the SOP[3:0] pins are sampled. This is a device

internal pentameter. Sampling happens when the internally generated supplies are

stable. For information only. Refer to TSU_SOP and TH_SOP parameters for application

usage.

–

μs

tSU_SOP

Setup time for SOP relative to PORz assertion.

–

μs

tH_SOP

Hold time for SOP relative to WARMRSTn deassertion.

–

μs

tWARMRSTn

Time from PORz de-assertion until the device de-asserts the WARMRESETn signal.

2.0

–

(1)

When using 1.8V OSPI flash, there is a minimum tDELAY_3V3 value of 50μs.

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SPRSPA7C – SEPTEMBER 2024 – REVISED JULY 2025

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