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AM261...ZEJQ1 数据表(PDF) 162 Page - Texas Instruments |
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AM261...ZEJQ1 数据表(HTML) 162 Page - Texas Instruments |
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162 / 218 page  6.11.5.13.2.3.1.3 OSPI1 Switching Characteristics - PHY SDR Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT O7 tc(CLK) Cycle time, OSPI_CLK 12.5 ns O8 tw(CLKL) Pulse duration, OSPI_CLK low 0.475P(1) - 0.3 ns O9 tw(CLKH) Pulse duration, OSPI_CLK high 0.475P(1) - 0.3 ns O10 td(CSn-CLK) Delay time, OSPI_CSn[1:0] active edge to OSPI_CLK rising edge 0.475P(1) + (0.975 × M(2) × R(4)) - 1 0.525P(1) + (1.025 × M(2) × R(4)) + 1 ns O11 td(CLK-CSn) Delay time, OSPI_CLK rising edge to OSPI_CSn[1:0] inactive edge 0.475P(1) + (0.975 × N(3) × R(4)) - 1 0.525P(1) + (1.025 × N(3) × R(4)) + 1 ns O12 td(CLK-D) Delay time, OSPI_CLK active edge to OSPI_D[7:0] transition 1.8V –1.6 –3.9 ns 3.3V –2.12 –5.2 ns (1) P = CLK cycle time = SCLK period in ns (2) M = OSPI_DEV_DELAY_REG[D_INIT_FLD] (3) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD] (4) R = REFCLK cycle time in ns tO9t tO8t tO7t tO11t O12 O10 OSPI_CSn OSPI_CLK OSPI_D[i:0] Figure 6-58. OSPI Switching Characteristics – PHY SDR 6.11.5.13.2.3.2 OSPI1 PHY DDR Timing 6.11.5.13.2.3.2.1 OSPI1 DLL Delay Mapping for PHY DDR Timing Modes MODE OSPI_PHY_CONFIGURATION_REG BIT FIELD DELAY VALUE Transmit 1.8V PHY_CONFIG_TX_DLL_DELAY_FLD 0x1E 3.3V PHY_CONFIG_TX_DLL_DELAY_FLD 0x1E Receive 1.8V, DQS PHY_CONFIG_RX_DLL_DELAY_FLD 0x14 3.3V, DQS PHY_CONFIG_RX_DLL_DELAY_FLD 0x19 1.8V, DDR with External Board Loopback PHY_CONFIG_RX_DLL_DELAY_FLD 0x64 3.3V, DDR with External Board Loopback PHY_CONFIG_RX_DLL_DELAY_FLD 0x69 AM2612, AM2611, AM2611-Q1, AM2612-Q1 SPRSPA7C – SEPTEMBER 2024 – REVISED JULY 2025 www.ti.com 162 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: AM2612 AM2611 AM2611-Q1 AM2612-Q1 |
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