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AM261...ZEJQ1 数据表(PDF) 163 Page - Texas Instruments |
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AM261...ZEJQ1 数据表(HTML) 163 Page - Texas Instruments |
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163 / 218 page  6.11.5.13.2.3.2.2 OSPI1 Timing Requirements - PHY DDR Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT O15 tsu(D-LBCLK) Setup time, OSPI_D[7:0] valid before active OSPI_DQS edge 1.8V, DDR with DQS 0.400 ns 3.3V, DDR with DQS 0.800 ns 1.8V, DDR with External Board Loopback 6 ns 3.3V, DDR with External Board Loopback 7 ns O16 th(LBTCLK-D) Hold time, OSPI_D[7:0] valid after active OSPI_DQS edge 1.8V, DDR with DQS 0.500 ns 3.3V, DDR with DQS 0.400 ns 1.8V, DDR with External Board Loopback 0 ns 3.3V, DDR with External Board Loopback 0 ns tO16t tO16t O15 O15 OSPI_DQS OSPI_D[i:0] Figure 6-59. OSPI Timing Requirements – PHY DDR with External Board Loopback or DQS 6.11.5.13.2.3.2.3 OSPI1 Switching Characteristics - PHY DDR Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT O1 tc(CLK) Cycle time, OSPI_CLK 12.5 ns O2 tw(CLKL) Pulse duration, OSPI_CLK low 0.475P(1) - 0.3 ns O3 tw(CLKH) Pulse duration, OSPI_CLK high 0.475P(1) - 0.3 ns O4 td(CSn-CLK) Delay time, OSPI_CSn[1:0] active edge to OSPI_CLK rising edge 0.475P(1) - (0.975 × M(2) × R(4)) 0.525P(1) - (1.025 × M(2) × R(4)) + 7 ns O5 td(CLK-CSn) Delay time, OSPI_CLK rising edge to OSPI_CSn[1:0] inactive edge 0.475P(1) + (0.975 × N(3) × R(4)) - 7 0.525P(1) + (1.025 × N(3) × R(4)) ns O6 td(CLK-D) Delay time, OSPI_CLK active edge to OSPI_D[7:0] transition 1.8V –1.5 –3.7 ns 3.3V –1.5 –3.7 ns (1) P = OSPI_CLK cycle time = SCLK period in ns (2) M = OSPI_DEV_DELAY_REG[D_INIT_FLD] (3) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD] (4) R = REFCLK cycle time in ns www.ti.com AM2612, AM2611, AM2611-Q1, AM2612-Q1 SPRSPA7C – SEPTEMBER 2024 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 163 Product Folder Links: AM2612 AM2611 AM2611-Q1 AM2612-Q1 |
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