M54HC77

M74HC77

October 1992

4-BIT D-TYPE LATCH

B1R

(Plastic Package)

ORDER CODES :

M54HC77F1R

M74HC77M1R

M74HC77B1R

M74HC77C1R

F1R

(Ceramic Package)

M1R

(Micro Package)

C1R

(Chip Carrier)

PIN CONNECTIONS (top view)

NC =

No Internal

Connection

INPUT AND OUTPUT EQUIVALENT CIRCUIT

.

HIGH SPEED

.

LOW POWER DISSIPATION

.

HIGH NOISE IMMUNITY

.

OUTPUT DRIVE CAPABILITY

10 LSTTL LOADS

.

SYMMETRICAL OUTPUT IMPEDANCE

.

BALANCED PROPAGATION DELAYS

.

WIDE OPERATING VOLTAGE RANGE

.

PIN AND FUNCTION COMPATIBLE WITH

54/74LS77

The M54/74HC77 is a high speed CMOS 4-BIT D-

TYPE LATCH fabricated in silicon gate C

nology. It has the same high speed performance of

LSTTL combined with true CMOS low power con-

sumption. It contains two groups of 2-bit latches con-

trolled by an enable input (G1

• 2or G3 • 4). These

two latch groups can be used in different circuits. The

data applied to the data inputs (1D, 2D, or 3D, 4D) are

transfered to the Q outputs (1Q, 2Q, or 3Q, 4Q) re-

spectively when the enable input (G1

• 2or G3 • 4) is

taken high. The Q outputs will follow the data inputs

as long as the enable input is kept high. When the en-

able input is taken low, the information data applied to

the data inputs is retained at the Q outputs. All inputs

are equipped with protection circuits against static dis-

charge and transient excess voltage.

DESCRIPTION

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