M54/74HC620

M54/74HC623

October 1992

HC620 3 STATE INVERTING HC623 3 STATE NON INVERTING

OCTAL BUS TRANSCEIVER

B1R

(Plastic Package)

ORDER CODES :

M54HCXXXF1R

M74HCXXXM1R

M74HCXXXB1R

M74HCXXXC1R

F1R

(Ceramic Package)

M1R

(Micro Package)

C1R

(Chip Carrier)

PIN CONNECTIONS (top view)

NC =

No Internal

Connection

DESCRIPTION

.

HIGH SPEED

.

LOW POWER DISSIPATION

.

HIGH NOISE IMMUNITY

.

OUTPUT DRIVE CAPABILITY

15 LSTTL LOADS

.

SYMMETRICAL OUTPUT IMPEDANCE

.

BALANCED PROPAGATION DELAYS

.

WIDE OPERATING VOLTAGE RANGE

.

PIN AND FUNCTION COMPATIBLE

WITH LS620/623

The M54/74HC620/623 are high speed CMOS

OCTAL BUS TRANSCEIVERS fabricated in silicon

gate C

speed performance of LSTTL combined with true

CMOS low power consumption.

These octal bus transceivers are designed for asyn-

chronous two-way communication between data

buses. The control function implementation allows

maximum flexibility in timing.

These devices allow data transmission from the A

bus to B bus or from the B to the A bus depending

upon the logic levels at the enable inputs (GBA and

GAB). The enable inputs can be used to disable the

device so that the buses are effectively isolated.

The dual-enable configuration gives these devices

the capability to store data by simultaneous enabling

of GBA and GAB.

Each output reinforces its input in this transceiver

configuration. Thus, when both control inputs are

enabled and all other data sources to the two sets

of bus lines are at high impedance, both sets of bus

lines (16 in all) will remain at their last states. The 8-

bit codes appearing on the two sets of buses will be

identical for the ’HC623 or complementary for the

’HC620. All inputs are equipped with protection cir-

cuits against static discharge and transient excess

voltage.

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