M54/74HCT373

M54/74HCT533

October 1993

HCT373 NON INVERTING - HCT533 INVERTING

OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT

B1R

(Plastic Package)

ORDER CODES :

M54HCTXXXF1R

M74HCTXXXM1R

M74HCTXXXB1R

M74HCTXXXC1R

F1R

(Ceramic Package)

M1R

(Micro Package)

C1R

(Chip Carrier)

PIN CONNECTION (top view)

.

HIGH SPEED

.

LOW POWER DISSIPATION

.

COMPATIBLE WITH TTL OUTPUTS

.

OUTPUT DRIVE CAPABILITY

15 LSTTL LOADS

.

SYMMETRICAL OUTPUT IMPEDANCE

.

BALANCED PROPAGATION DELAYS

.

PIN AND FUNCTION COMPATIBLE

WITH 54/74LS373/533

DESCRIPTION

The M54/74HCT373 and M54HCT533 are high

speed CMOS OCTAL LATCH WITH 3-STATE

OUTPUTS fabricated with in silicon gate C

technology.

These ICs achive the high speed operation similar

to equivalent LSTTL while maintaning the CMOS

low power dissipation.

These 8 bit D-Type latches are controlled by a latch

enable input (LE) and a output enable input (OE).

While the LE input is held at a high level, the Q

outputs will follow the data input precisely or

inversely. When the LE is taken low, the Q outputs

will be latched precisely or inversely at the logic level

of D input data. While the OE input is at low level,

the eight outputs will be in a normal logic state (high

or low logic level) and while high level the outpts will

be in a high impedance state. The application

designer has a choise of combination of inverting

and non inverting outputs. The three state output

configuration and the wide choise of outline make

bus organized system simple.

These integrated circuits have input and output

characteristics that are fully compatible with 54/74

LSTTL logic families. M54/74HCT devices are

designed to directly interface HSC

with TTL and NMOS components. They are also

plug in replacements for LSTTL devices giving a

reduction of power consumption. All inputs are

equipped with protection circuits against discharge

and transient excess voltage.

HCT373

HCT533

HCT373

HCT533

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