Ultra Fast USB 2.0 Multi-Format Flash Media Controller

Datasheet

SMSC USB2240/USB2241

13

Revision 2.6 (05-08-08)

DATASHEET

Chapter 5 Pin Descriptions

This section provides a detailed description of each signal. The signals are arranged in functional

groups according to their associated interface.

The “n” symbol in the signal name indicates that the active, or asserted, state occurs when the signal

is at a low voltage level. When “n” is not present before the signal name, the signal is asserted at the

high voltage level.

The terms assertion and negation are used exclusively. This is done to avoid confusion when working

with a mixture of “active low” and “active high” signals. The term assert, or assertion, indicates that a

signal is active, independent of whether that level is represented by a high or low voltage. The term

negate, or negation, indicates that a signal is inactive.

5.1

Pin Descriptions

Table 5.1 USB2240/USB2241 36-Pin QFN Pin Descriptions

NAME

SYMBOL

36-PIN

QFN

BUFFER

TYPE

DESCRIPTION

xD INTERFACE (APPLIES ONLY TO USB2240)

xD Data

xD_D[7:0]

20

23

25

30

4

5

7

8

I/O12PD

The bi-directional data signal has an internal weak

pull-down resistor.

xD Write

Protect

xD_nWP

9

O12PD

This pin is an active low write protect signal for the

xD device. This pin has a weak pull-down resistor

that is permanently enabled.

xD Address

Strobe

xD_ALE

10

O12PD

This pin is an active high Address Latch Enable

signal for the xD device.

This pin has a weak pull-down resistor that is

permanently enabled.

xD Command

Strobe

xD_CLE

11

O12PD

This pin is an active high Command Latch Enable

signal for the xD device.

This pin has a weak pull-down resistor that is

permanently enabled.

xD Read

Enable

xD_nRE

16

O12PU

This pin is an active low read strobe signal for xD

device.

When using the internal FET, this pin has an internal

weak pull-up resistor that is tied to the output of the

internal Power FET, and is controlled by the SM_PU

bit of the SM_CTL register.

If an external FET is used (Internal FET is disabled),

then the internal pull-up is not available (external

pull-ups must be used).