USB2250 datasheet(19/36 Pages) SMSC

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Ultra Fast USB 2.0 Multi-Format Flash Media Controller

Datasheet

SMSC USB2250/51/59

Revision 2.6 (05-08-08)

DATASHEET

MEMORY / IO INTERFACE

Memory Data

Bus

MD[7:0]

I/O12

These signals are used to transfer data between

the internal CPU and the external program

memory.

Note:

These pins have internal weak pull-up

resistors that are controlled by the

MD_PU_DIS bit of the

PWR_MGMT_CTL1 register.

Memory

Address Bus

MA16

O12

These signals address memory locations within

the external memory. MA16 is a bit generated by

the ROM Mapper.

Memory

Address Bus

MA[15:2]

107

113

111

109

106

108

110

112

114

116

O12

These signals address memory locations within

the external memory.

Note: USB2259 requires that MA2 be tied to

3.3V via a 10K resistor.

Memory

Address Bus

MA1[1:0] /

CLK_

SEL1[1:0]

O12

MA[1:0]: These signals address memory locations

within the external memory.

I/O12PD

CLK_SEL[1:0]: During nRESET assertion, these

pins will select the operating frequency of the

external clock, and the corresponding weak pull-

down resistors are enabled. When nRESET is

negated, the value on these pins will be internal

latched and these pins will revert to MA[1:0]

functionality; the internal pull-downs will be

disabled.

CLK_SEL[1:0] = '00'. 24MHz

CLK_SEL[1:0] = '01'. RESERVED

CLK_SEL[1:0] = '10'. RESERVED

CLK_SEL[1:0] = '11'. 48MHz

Note:

If the latched value is '1', then the

corresponding MA pin is tri-stated when

the chip is in the powerdown state.

If the latched value is '0', then the corresponding

MA pin will function identically to the MA[15:3]

pins at all times (other than during nRESET

assertion).

Memory Write

Strobe

nMWR

O12

Program Memory Write; active low

Memory Read

Strobe

nMRD

115

O12

Program Memory Read; active low

Table 5.1 USB2250/51/59 128-Pin VTQFP Pin Descriptions (continued)

NAME

SYMBOL

128-PIN

VTQFP

BUFFER

TYPE

DESCRIPTION

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