M58LW032C datasheet(13/61 Pages) STMICROELECTRONICS

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M58LW032C

BUS OPERATIONS

There are six standard bus operations that control

the device. These are Address Latch, Bus Read,

Bus Write, Output Disable, Power-Down and

Standby. See Table 2, Bus Operations, for a sum-

mary.

Typically glitches of less than 5ns on Chip Enable

or Write Enable are ignored by the memory and do

not affect Bus Write operations.

Address Latch. Address latch operations input

valid addresses.

A valid bus operation involves setting the desired

address on the Address Inputs, setting Chip En-

able and Latch Enable Low, VIL and keeping Write

Enable High, VIH; the address is latched on the ris-

ing edge of Address Latch.

Bus Read. Bus Read operations are used to out-

put the contents of the Memory Array, the Elec-

tronic Signature, the Status Register, the Common

Flash Interface and the Block Protection Status.

A valid bus operation involves setting the desired

address on the Address Inputs, applying a Low

signal, VIL, to Chip Enable, Output Enable and

Latch Enable and keeping Write Enable High, VIH.

The data read depends on the previous command

written to the memory (see Command Interface

section). See Figures 11, 12, 13, 18 and 19 Read

AC Waveforms, and Tables 15, 16, 17 and 20

Read AC Characteristics, for details of when the

output becomes valid.

Bus Write. Bus Write operations write Com-

mands to the memory or latch addresses and input

data to be programmed.

A valid Bus Write operation begins by setting the

desired address on the Address Inputs and setting

Latch Enable Low, VIL. The Address Inputs are

latched by the Command Interface on the rising

edge of Chip Enable or Write Enable, whichever

occurs first. The Data Inputs/Outputs are latched

by the Command Interface on the rising edge of

Chip Enable or Write Enable, whichever occurs

first. Output Enable must remain High, VIH, during

the Bus Write operation.

See Figures 14, 15, 16 and 17, Write AC Wave-

forms, and Tables 18 and 19, Write AC Character-

istics, for details of the timing requirements.

Output Disable. The The Data Inputs/Outputs

are high impedance when the Output Enable is at

VIH.

Power-Down. The memory is in Power-Down

mode when Reset/Power-Down, RP, is Low. The

power consumption is reduced to the Power-Down

level, IDD2, and the outputs are high impedance,

independent of Chip Enable, Output Enable or

Write Enable.

Standby. Standby disables most of the internal

circuitry, allowing a substantial reduction of the

current consumption. The memory is in standby

when Chip Enable is at VIH. The power consump-

tion is reduced to the standby level IDD1 and the

outputs are set to high impedance, independently

from the Output Enable or Write Enable inputs.

If Chip Enable switches to VIH during a program or

erase operation, the device enters Standby mode

when finished.

Table 2. Bus Operations

Note: 1. X = Don’t Care VIL or VIH.

2. Depends on G

Operation

A1-A21

DQ0-DQ15

Address Latch

VIL

VIH

VIL

Address

Data Output or Hi-Z (2)

Bus Read

VIL

VIH

VIL

Address

Data Output

Bus Write

VIL

VIH

VIL

VIH

VIL

Address

Data Input

Output Disable

VIL

VIH

High Z

Power-Down

VIL

High Z

Standby

VIH

High Z

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