M68AW064F

8/18

OPERATION

The M68AW064F has a Chip Enable power down

feature which invokes an automatic standby mode

whenever either Chip Enable is de-asserted

(E = High) or LB and UB are de-asserted (LB and

UB = High). An Output Enable (G) signal provides

a high speed tri-state control, allowing fast read/

write cycles to be achieved with the common I/O

data bus. Operational modes are determined by

device control inputs W, E, LB and UB as summa-

rized in the Operating Modes table (see Table 6).

Table 6. Operating Modes

Read Mode

The M68AW064F is in the Read mode whenever

Write Enable (W) is High with Output Enable (G)

Low, and Chip Enable (E) is asserted. This pro-

vides access to data from eight or sixteen, de-

pending on the status of the signal UB and LB, of

the 1,048,576 locations in the static memory array,

specified by the 16 address inputs. Valid data will

be available at the eight or sixteen output pins

ing G is Low and E is Low. If Chip Enable or Output

Enable access times are not met, data access will

Figure 7. Address Controlled, Read Mode AC Waveforms

Note: E = Low, G = Low, W = High, UB = Low and/or LB = Low.

Operation

E

W

G

LB

UB

DQ0-DQ7

DQ8-DQ15

Power

Deselected/Power-down

XXXX

Hi-Z

Hi-Z

Deselected/Power-down

X

X

X

Hi-Z

Hi-Z

Lower Byte Read

Data Output

Hi-Z

Lower Byte Write

X

Data Input

Hi-Z

Output Disabled

X

X

Hi-Z

Hi-Z

Output Disabled

X

X

Hi-Z

Hi-Z

Upper Byte Read

Hi-Z

Data Output

Upper Byte Write

X

Hi-Z

Data Input

Word Read

Data Output

Data Output

Word Write

X

Data Input

Data Input

AI04876

tAVAV

tAVQV

tAXQX

A0-A15

DQ0-DQ15

VALID

DATA VALID