RTL8181
CONFIDENTIAL
v1.0
7
WLTXRX
LED1B
O
64
T18
WLAN Tx/Rx traffic indicator or JTAG CLK
RF Interface for Intersil
RIFSCK
O
66
R20
3-wire Bus Clock
RIFSD
O
67
P19
3-wire Bus Data
RFLE
O
68
P18
3-wire Bus Enable
IFLE/AGC
SET
O
70
N18
IF_LE of the Intersil Chipset: PLL Synthesizer Serial Interface Latch Enable
Control. CMOS output.
CALEN/
AGCRESE
T
O
71
P20
CAL_EN of the Intersil Chipset: CMOS output for activation of DC offset adjust
circuit. A rising edge activates the calibration cycle, which completes within a
programmable time and holds the calibration while this pin is held high. In
applications where the synthesizer is not used, this pin needs to be grounded.
LNA_HL
O
73
M19
Drive to the RF AGC Stage Attenuator: CMOS digital.
ANTSELP O
75
M20
Antenna Select +: The antenna selects signal changes state as the receiver
switches from antenna to antenna during the acquisition process in the antenna
diversity mode. This is a complement for ANTSELN for differential drive of
ant enna switches.
ANTSELN O
76
L18
Antenna Select -: The antenna selects signal changes state as the receiver
switches from antenna to antenna during the acquisition process in the antenna
diversity mode. This is a complement for ANTSELP for differential drive of
antenna switches.
TRSWP
TRSWN
O
O
78
79
L19
L20
Transmit/Receive Control
VCOPDN/
PHITXI
O
81
K20
Output Pin as VCO VCC Power Enable/D isable.
PAPE
O
82
K19
Transmit PA Power Enable
PE1/PHIT
XQ
O
84
K18
The combination of PE1 and PE2 are as follows:
00: Power Down State, PLL Registers in Save Mode, Inactive PLL, Active Serial
11: Receive State, Active PLL
10: Transmit State, Active PLL
01: Inactive Transmit and Receive States, Active PLL, Active Serial Interface
PE2
O
85
J20
Output Pin as PE2: Refer to PE1 description.
RXIP
RXIN
AI
AI
110
109
B19
B20
Receive (Rx) In-phase Differential Analog Data
RXQP
RXQN
AI
AI
106
C18,C19
Receive (Rx) Quadrature Differential Analog Data
RSSI
AI
105
D17
Analog Input to the Receive Power A/D Converter for AGC Control
TXDET
AI
102
D18
Input to the Transmit Power A/D Converter for Transmit AGC Control
VREFI
AI
101
C20
Voltage Reference for ADC and DAC
TXIP
TXIN
AO
AO
97
96
E19,F18
Transmit (TX) In-phase Differential Analog Data
TXQP
TXQN
AO
AO
94
93
E20,F20
Trans mit (TX) Quadrature Differential Analog Data
TXAGC
AO
91
F19
Analog Drive to the Transmit IF Power Control
RXAGC
AO
90
G18
Analog Drive to the Receive IF AGC Control
RF Interface for RFMD
RIFSCK
O
66
R20
3-wire Bus Clock: The serial clock output, with resistive dividers on board to
allow programming from +5V levels.
RIFSD
O
67
P19
3-wire Bus Data: Serial data output, with resistive dividers on board to allow
programming from +5V levels.
RFLE
O
68
P18
3-wire Bus Enable: Enable serial port output, with resistive dividers on board to
allow programming from +5V levels.
IFLE/AGC
SET
X*
70
N18
Not used in the RFMD RF chipset.
CALEN/
AGCRESE
T
X
71
P20
Not used in the RFMD RF chipset.
LNA_HL
O
73
M19
RF2494 Gain Select: Digital output.
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